LH28F008SCT-V12 Sharp Electronics, LH28F008SCT-V12 Datasheet - Page 24

• Manufacturer Part Number: LH28F008SCT-V12
• Manufacturer: Sharp Electronics

Specifications of LH28F008SCT-V12

• Cell Type: NOR
• Density: 8Mb
• Access Time (max): 120ns
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 20b
• Operating Supply Voltage (typ): 5V
• Operating Temp Range: 0C to 70C
• Package Type: TSOP-I
• Sync/async: Asynchronous
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Word Size: 8b
• Number Of Words: 1M
• Supply Current: 50mA
• Mounting: Surface Mount
• Pin Count: 40
• Lead Free Status / Rohs Status: Not Compliant

operation is restored. Device power-off or RP#
transitions to V
The CUI latches commands issued by system
software and is not altered by V
transitions or WSM actions. Its state is read array
mode upon power-up, after exit from deep power-
down or after V
After
configuration, even after V
V
via the Read Array command if subsequent access
to the memory array is desired.
5.6 Power-Up/Down Protection
The device is designed to offer protection against
accidental block erasure, byte writing, or lock-bit
configuration during power transitions. Upon power-
up, the device is indifferent as to which power
supply (V
circuitry resets the CUI to read array mode at
power-up.
A system designer must guard against spurious
writes for V
active. Since both WE# and CE# must be low for a
command write, driving either to V
writes. The CUI’s two-step command sequence
architecture provides added level of protection
against data alteration.
In-system block lock and unlock capability prevents
inadvertent data alteration. The device is disabled
while RP# = V
state.
PPLK
, the CUI must be placed in read array mode
block
PP
CC
or V
IL
erase,
CC
voltages above V
IL
clear the status register.
regardless of its control inputs
transitions below V
CC
) powers-up first. Internal
byte
PP
write,
transitions down to
LKO
LKO
IH
when V
PP
or
will inhibit
.
or CE#
lock-bit
PP
is
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5.7 Power Consumption
When designing portable systems, designers must
consider battery power consumption not only during
device operation, but also for data retention during
system idle time. Flash memory’s nonvolatility
increases usable battery life because data is
retained when system power is removed.
In addition, deep power-down mode ensures
extremely low power consumption even when
system power is applied. For example, portable
computing products and other power sensitive
applications that use an array of devices for solid-
state storage can consume negligible power by
lowering RP# to V
access is again needed, the devices can be read
following the t
required after RP# is first raised to V
6.2.4 through 6.2.6 "AC CHARACTERISTICS -
READ-ONLY and WRITE OPERATIONS" and
Fig. 12, Fig. 13 and Fig. 14 for more information.
PHQV
IL
and t
standby or sleep modes. If
LH28F008SC-V/SCH-V
PHWL
wake-up cycles
IH
. See Section