LH28F008SCR-L85 Sharp Electronics, LH28F008SCR-L85 Datasheet - Page 11

• Manufacturer Part Number: LH28F008SCR-L85
• Manufacturer: Sharp Electronics

Specifications of LH28F008SCR-L85

• Cell Type: NOR
• Density: 8Mb
• Access Time (max): 85ns
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 20b
• Operating Supply Voltage (typ): 5V
• Operating Temp Range: 0C to 70C
• Package Type: TSOP
• Program/erase Volt (typ): 3.3/5/12V
• Sync/async: Asynchronous
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Word Size: 8b
• Number Of Words: 1M
• Supply Current: 50mA
• Mounting: Surface Mount
• Pin Count: 40
• Lead Free Status / Rohs Status: Not Compliant

3 BUS OPERATION
The local CPU reads and writes flash memory
in-system. All bus cycles to or from the flash memory
conform to standard microprocessor bus cycles.
3.1 Read
Information can be read from any block, identifier
codes, or status register independent of the V
voltage. RP# can be at either V
The first task is to write the appropriate read mode
command (Read Array, Read Identifier Codes, or
Read Status Register) to the CUI. Upon initial device
power-up or after exit from deep power-down mode,
the device automatically resets to read array mode.
Four control pins dictate the data flow in and out of
the component: CE#, OE#, WE#, and RP#. CE# and
OE# must be driven active to obtain data at the
outputs. CE# is the device selection control, and
when active enables the selected memory device.
OE# is the data output (DQ
active drives the selected memory data onto the I/O
bus. WE# must be at V
V
3.2 Output Disable
With OE# at a logic-high level (V
outputs are disabled. Output pins DQ
placed in a high-impedance state.
3.3 Standby
CE# at a logic-high level (V
standby mode which substantially reduces device
power consumption. DQ
a high-impedance state independent of OE#. If
deselected during block erase, byte write, or lock-bit
configuration, the device continues functioning, and
HH
. Figure 15 illustrates a read cycle.
IH
0
-DQ
and RP# must be at V
0
IH
-DQ
7
) places the device in
IH
outputs are placed in
7
or V
) control and when
HH
IH
), the device
.
0
-DQ
7
IH
are
LHF08CTF
PP
or
consuming
completes.
3.4 Deep Power-Down
RP# at V
In read modes, RP#-low deselects the memory,
places output drivers in a high-impedance state and
turns off all internal circuits. RP# must be held low for
a minimum of 100 ns. Time t
return from power-down until initial memory access
outputs are valid. After this wake-up interval, normal
operation is restored. The CUI is reset to read array
mode and status register is set to 80H.
During
configuration
operation. RY/BY# remains low until the reset
operation is complete. Memory contents being
altered are no longer valid; the data may be partially
erased or written. Time t
goes to logic-high (V
be written.
As with any automated device, it is important to
assert RP# during system reset. When the system
comes out of reset, it expects to read from the flash
memory. Automated flash memories provide status
information when accessed during block erase, byte
write, or lock-bit configuration modes. If a CPU reset
occurs with no flash memory reset, proper CPU
initialization may not occur because the flash memory
may be providing status information instead of array
data. SHARP’s flash memories allow proper CPU
initialization following a system reset through the use
of the RP# input. In this application, RP# is controlled
by the same RESET# signal that resets the system
CPU.
IL
block
initiates the deep power-down mode.
active
modes,
erase,
IH
power
) before another command can
RP#-low
PHWL
byte
PHQV
until
is required after RP#
write,
will
is required after
the
or
abort
operation
Rev. 1.3
lock-bit
the
8