LH28F008SCR-L85 Sharp Electronics, LH28F008SCR-L85 Datasheet - Page 7

• Manufacturer Part Number: LH28F008SCR-L85
• Manufacturer: Sharp Electronics

Specifications of LH28F008SCR-L85

• Cell Type: NOR
• Density: 8Mb
• Access Time (max): 85ns
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 20b
• Operating Supply Voltage (typ): 5V
• Operating Temp Range: 0C to 70C
• Package Type: TSOP
• Program/erase Volt (typ): 3.3/5/12V
• Sync/async: Asynchronous
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Word Size: 8b
• Number Of Words: 1M
• Supply Current: 50mA
• Mounting: Surface Mount
• Pin Count: 40
• Lead Free Status / Rohs Status: Not Compliant

Individual block locking uses a combination of bits,
sixteen block lock-bits and a master lock-bit, to lock
and unlock blocks. Block lock-bits gate block erase
and byte write operations, while the master lock-bit
gates
configuration operations (Set Block Lock-Bit, Set
Master
commands) set and cleared lock-bits.
The status register indicates when the WSM’s block
erase, byte write, or lock-bit configuration operation is
finished.
The RY/BY# output gives an additional indicator of
WSM activity by providing both a hardware signal of
status (versus software polling) and status masking
(interrupt masking for background block erase, for
example). Status polling using RY/BY# minimizes
both CPU overhead and system power consumption.
When low, RY/BY# indicates that the WSM is
performing a block erase, byte write, or lock-bit
configuration. RY/BY#-high indicates that the WSM is
ready for a new command, block erase is suspended
(and byte write is inactive), byte write is suspended,
or the device is in deep power-down mode.
block
Lock-Bit,
lock-bit
and
Clear
modification.
Block
Lock-Bits
Lock-bit
LHF08CTF
The access time is 85ns (t
temperature range (0°C to +70°C) and V
voltage range of 4.75V-5.25V. At lower V
the access times are 90ns (4.5V-5.5V), 120ns
(3.0V-3.6V) and 150ns (2.7V-3.6V).
The
substantially reduces active current when the device
is in static mode (addresses not switching). In APS
mode, the typical I
When CE# and RP# pins are at V
standby mode is enabled. When the RP# pin is at
GND, deep power-down mode is enabled which
minimizes power consumption and provides write
protection during reset. A reset time (t
required from RP# switching high until outputs are
valid. Likewise, the device has a wake time (t
from RP#-high until writes to the CUI are recognized.
With RP# at GND, the WSM is reset and the status
register is cleared.
The device is available in 44-lead PSOP (Plastic
Small Outline Package). Pinout is shown in Figure 2.
Automatic
CCR
Power
current is 1 mA at 5V V
AVQV
Savings
) over the commercial
CC
, the I
(APS)
CC
CC
CC
PHQV
voltages,
Rev. 1.3
CC
feature
CMOS
supply
PHEL
.
) is
4
)