TB28F004S5-100 Intel, TB28F004S5-100 Datasheet - Page 15

• Manufacturer Part Number: TB28F004S5-100
• Manufacturer: Intel

Specifications of TB28F004S5-100

• Cell Type: NOR
• Density: 4Mb
• Access Time (max): 100ns
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 19b
• Operating Supply Voltage (typ): 5V
• Operating Temp Range: -40C to 85C
• Package Type: SOP
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Word Size: 8b
• Number Of Words: 512K
• Mounting: Surface Mount
• Pin Count: 44
• Lead Free Status / Rohs Status: Not Compliant

Block preconditioning, erase, and verify are handled
internally by the WSM (invisible to the system).
After the two-cycle block erase sequence is written,
the device automatically outputs status register
data when read (see Figure 6). The CPU can detect
block erase completion by analyzing the RY/BY#
pin or status register bit SR.7.
When the block erase is complete, status register
bit SR.5 should be checked. If a block erase error is
detected, the status register should be cleared
before system software attempts corrective actions.
The CUI remains in read status register mode until
a new command is issued.
This two-step command sequence of set-up
followed by execution ensures that block contents
are not accidentally erased. An invalid Block Erase
command sequence will result in both status
register bits SR.4 and SR.5 being set to “1.” Also,
reliable block erasure can only occur when
V
this high voltage, block contents are protected
against erasure. If block erase is attempted while
V
Successful
corresponding block lock-bit be cleared or, if set,
that RP# = V
the corresponding block lock-bit is set and
RP# = V
SR.5 will be set to “1.” Block erase operations with
V
should not be attempted.
4.6
Program is executed by a two-cycle command
sequence.
alternate 10H) is written, followed by a second write
that specifies the address and data (latched on the
rising edge of WE#). The WSM then takes over,
controlling the program and write verify algorithms
internally. After the program sequence is written,
the device automatically outputs status register
data when read (see Figure 7). The CPU can detect
the completion of the program event by analyzing
the RY/BY# pin or status register bit SR.7.
When program is complete, status register bit SR.4
should be checked. If program error is detected, the
status register should be cleared. The internal WSM
verify only detects errors for “1”s that do not
successfully program to “0”s. The CUI remains in
read status register mode until it receives another
command.
CC
PP
IH
PRELIMINARY
< RP# < V
= V
V
CC1/2
PPLK
IH
Program Command
, the block erase will fail, and SR.1 and
Program setup (standard 40H
, SR.3 and SR.5 will be set to “1.”
HH
and V
block
. If block erase is attempted when
HH
PP
produce spurious results and
erase
= V
PPH1/2
requires
. In the absence of
that
the
or
Reliable programs only occurs when V
and V
voltage, memory contents are protected against
programs. If program is attempted while V
V
SR.3 and SR.5 will be set to “1.”
Successful
corresponding block lock-bit be cleared or, if set,
that RP# = V
corresponding block lock-bit is set and RP# = V
program will fail, and SR.1 and SR.4 will be set to
“1.” Program operations with V
produce spurious results and should not be
attempted.
4.7
The Block Erase Suspend command allows
block-erase interruption to read data from or
program data to another block of memory. Once the
block erase process starts, writing the Block Erase
Suspend
suspend
predetermined point in the algorithm. The device
outputs status register data when read after the
Block Erase Suspend command is written. Polling
status register bits SR.7 and SR.6 can determine
when
suspended (both will be set to “1”). RY/BY# will also
transition to V
block erase suspend latency.
At this point, a Read Array command can be written
to read data from blocks other than that which is
suspended. A Program command sequence can
also be issued during erase suspend to program
data in other blocks. Using the Program Suspend
command (see Section 4.8), a program operation
can also be suspended. During a program operation
with block erase suspended, status register bit
SR.7 will return to “0” and the RY/BY# output will
transition to V
indicate block erase suspend status.
The only other valid commands while block erase is
suspended are Read Status Register and Block
Erase Resume. After a Block Erase Resume
command is written to the flash memory, the WSM
will continue the block erase process. Status
register bits SR.6 and SR.7 will automatically clear
and RY/BY# will return to V
Resume
automatically outputs status register data when
read (see Figure 8). V
PPLK
, the operation will fail, and status register bits
PP
the
Block Erase Suspend
Command
= V
the
command
command
block
28F004S5, 28F008S5, 28F016S5
program
HH
PPH1/2
OL
OH
. If program is attempted when the
. However, SR.6 will remain “1” to
block
. Specification t
. In the absence of this high
erase
requests
PP
is
also
erase
must remain at V
written,
operation
OL
requires
WHRH2
. After the Erase
sequence
IH
that
< RP# < V
the
CC
defines the
the
has
that
= V
device
at
PPH1/2
WSM
PP
been
CC1/2
the
15
IH
HH
a
,