TB28F004S5-100 Intel, TB28F004S5-100 Datasheet - Page 18

• Manufacturer Part Number: TB28F004S5-100
• Manufacturer: Intel

Specifications of TB28F004S5-100

• Cell Type: NOR
• Density: 4Mb
• Access Time (max): 100ns
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 19b
• Operating Supply Voltage (typ): 5V
• Operating Temp Range: -40C to 85C
• Package Type: SOP
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Word Size: 8b
• Number Of Words: 512K
• Mounting: Surface Mount
• Pin Count: 44
• Lead Free Status / Rohs Status: Not Compliant

28F004S5, 28F008S5, 28F016S5
18
SR.7 = WRITE STATE MACHINE STATUS
SR.6 = ERASE SUSPEND STATUS
SR.5 = ERASE AND CLEAR LOCK-BITS
SR.4 = PROGRAM AND SET LOCK-BIT
SR.3 = V
SR.2 = PROGRAM SUSPEND STATUS
SR.1 = DEVICE PROTECT STATUS
SR.0 = RESERVED FOR FUTURE
WSMS
1 = Ready
0 = Busy
1 = Block Erase Suspended
0 = Block Erase in Progress/Completed
1 = Error in Block Erasure or Clear Lock-Bits
0 = Successful Block Erase or Clear Lock-Bits
1 = Error in Program or Set Master/Block
0 = Successful Program or Set Master/Block
1 = V
0 = V
1 = Program Suspended
0 = Program in Progress/Completed
1 = Master Lock-Bit, Block Lock-Bit and/or
0 = Unlock
7
Lock-Bit
STATUS
STATUS
Lock-Bit
RP# Lock Detected, Operation Abort
ENHANCEMENTS
PP
PP
PP
STATUS
Low Detect, Operation Abort
OK
ESS
6
ECLBS
5
Table 6. Status Register Definition
PSLBS
4
NOTES:
Check RY/BY# or SR.7 to determine block erase,
program, or lock-bit configuration completion.
SR.6–0 are invalid while SR.7 = “0.”
If both SR.5 and SR.4 are “1”s after a block erase or
lock-bit configuration attempt, an improper
command sequence was entered.
SR.3 does not provide a continuous indication of
V
V
bit configuration operation. SR.3 is not guaranteed
to reports accurate feedback only when V
V
SR.1 does not provide a continuous indication of
master and block lock-bit values. The WSM
interrogates the master lock-bit, block lock-bit, and
RP# only after a block erase, program, or lock-bit
configuration operation. It informs the system,
depending on the attempted operation, if the block
lock-bit is set, master lock-bit is set, and/or
RP#
SR.0 is reserved for future use and should be
masked out when polling the status register.
PP
PP
PPH1/2
VPPS
level. The WSM interrogates and indicates the
level only after a block erase, program, or lock-
3
.
V
HH
.
PSS
2
PRELIMINARY
DPS
1
PP
R
0