TB28F004S5-100 Intel, TB28F004S5-100 Datasheet - Page 6

• Manufacturer Part Number: TB28F004S5-100
• Manufacturer: Intel

Specifications of TB28F004S5-100

• Cell Type: NOR
• Density: 4Mb
• Access Time (max): 100ns
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 19b
• Operating Supply Voltage (typ): 5V
• Operating Temp Range: -40C to 85C
• Package Type: SOP
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Word Size: 8b
• Number Of Words: 512K
• Mounting: Surface Mount
• Pin Count: 44
• Lead Free Status / Rohs Status: Not Compliant

28F004S5, 28F008S5, 28F016S5
To protect programmed data, each block can be
locked. This block locking mechanism uses a
combination of bits, block lock-bits and a master
lock-bit, to lock and unlock individual blocks. The
block lock-bits gate block erase and program
operations, while the master lock-bit gates block
lock-bit configuration operations. Lock-bit config-
uration operations (Set Block Lock-Bit, Set Master
Lock-Bit, and Clear Block Lock-Bits commands) set
and clear lock-bits.
The status register and RY/BY# output indicate
whether or not the device is busy executing or
ready for a new command. Polling the status
register, system software retrieves WSM feedback.
The RY/BY# output gives an additional indicator of
WSM activity by providing a hardware status signal.
Like the status register, RY/BY#-low indicates that
the WSM is performing a block erase, program, or
lock-bit configuration. RY/BY#-high indicates that
the WSM is ready for a new command, block erase
is suspended (and program is inactive), program is
suspended, or the device is in deep power-down
mode.
6
4-Mbit: A - A
8-Mbit: A - A
16-Mbit: A - A
0
0
0
18
19
20
,
,
Address
Address
Counter
Buffer
Input
Latch
Decoder
Decoder
Y
X
Output
Buffer
Figure 1. Block Diagram
16-Mbit: Thirty-Two
64-Kbyte Blocks
8-Mbit: Sixteen
Comparator
4-Mbit: Eight
Y Gating
DQ - DQ
Identifier
Register
Register
Status
Data
0
7
The Automatic Power Savings (APS) feature
substantially reduces active current when the
device is in static mode (addresses not switching).
In APS mode, the typical I
When CE# and RP# pins are at V
component enters a CMOS standby mode. Driving
RP# to GND enables a deep power-down mode
which significantly reduces power consumption,
provides write protection, resets the device, and
clears the status register. A reset time (t
required from RP# switching high until outputs are
valid. Likewise, the device has a wake time (t
from RP#-high until writes to the CUI are
recognized.
1.3
The family of devices is available in 40-lead TSOP
(Thin Small Outline Package, 1.2 mm thick) and
44-lead PSOP (Plastic Small Outline Package).
Pinouts are shown in Figures 2 and 3.
Buffer
Input
Pinout and Pin Description
Write State
Command
Machine
Register
PRELIMINARY
CCR
Program/Erase
current is 1 mA.
Voltage Switch
I/O Logic
V
CE#
WE#
OE#
RP#
RY/BY#
V
V
GND
CC
PHQV
PP
CC
CC
, the
PHEL
) is
)