PA28F800BVT120 Intel, PA28F800BVT120 Datasheet - Page 10

• Manufacturer Part Number: PA28F800BVT120
• Manufacturer: Intel

Specifications of PA28F800BVT120

• Density: 8Mb
• Interface Type: Parallel
• Boot Type: Top
• Address Bus: 20/19Bit
• Operating Supply Voltage (typ): 3.3/5V
• Operating Temp Range: 0C to 70C
• Package Type: SOP
• Sync/async: Asynchronous
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 5.5V
• Word Size: 8/16Bit
• Number Of Words: 1M/512K
• Supply Current: 65mA
• Mounting: Surface Mount
• Pin Count: 44
• Lead Free Status / Rohs Status: Not Compliant

8-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
1.5
10
A
A
DQ
DQ
CE#
OE#
WE#
RP#
Symbol
0
9
–A
0
8
–DQ
–DQ
19
Pin Descriptions
7
15
INPUT/OUTPUT
INPUT/OUTPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
Type
ADDRESS INPUTS for memory addresses. Addresses are internally
latched during a write cycle. The 28F800 only has A
the 28F008B has A
ADDRESS INPUT: When A
During this mode, A
When BYTE# is at a logic low, only the lower byte of the signatures are
read. DQ
DATA INPUTS/OUTPUTS: Inputs array data on the second CE# and
WE# cycle during a Program command. Inputs commands to the
Command User Interface when CE# and WE# are active. Data is
internally latched during the Write cycle. Outputs array, intelligent
identifier and status register data. The data pins float to tri-state when the
chip is de-selected or the outputs are disabled.
DATA INPUTS/OUTPUTS: Inputs array data on the second CE# and
WE# cycle during a Program command. Data is internally latched during
the Write cycle. Outputs array data. The data pins float to tri-state when
the chip is de-selected or the outputs are disabled as in the byte-wide
mode (BYTE# = “0”). In the byte-wide mode DQ
lowest order address for data output on DQ
not include these DQ
CHIP ENABLE: Activates the device’s control logic, input buffers,
decoders and sense amplifiers. CE# is active low. CE# high de-selects
the memory device and reduces power consumption to standby levels. If
CE# and RP# are high, but not at a CMOS high level, the standby
current will increase due to current flow through the CE# and RP# input
stages.
OUTPUT ENABLE: Enables the device’s outputs through the data
buffers during a read cycle. OE# is active low.
WRITE ENABLE: Controls writes to the command register and array
blocks. WE# is active low. Addresses and data are latched on the rising
edge of the WE# pulse.
RESET/DEEP POWER-DOWN: Uses three voltage levels (V
V
boot block unlocking. It is backwards-compatible with the BX/BL/BV
products.
When RP# is at logic low, the device is in reset/deep power-down
mode, which puts the outputs at High-Z, resets the Write State Machine,
and draws minimum current.
When RP# is at logic high, the device is in standard operation.
When RP# transitions from logic-low to logic-high, the device defaults to
the read array mode.
When RP# is at V
programmed or erased. This overrides any control from the WP# input.
Table 2. 28F800/008B Pin Descriptions
HH
) to control two different functions: reset/deep power-down mode and
SEE NEW DESIGN RECOMMENDATIONS
15
/A
–1
is a don’t care in the signature mode when BYTE# is low.
HH
0
0
, the boot block is unlocked and can be
–A
decodes between the manufacturer and device IDs.
8
–DQ
19
.
Name and Function
9
15
is at V
pins.
HH
the signature mode is accessed.
0
–DQ
15
7
/A
. The 28F008B does
–1
0
–A
becomes the
18
pins, while
IL
, V
IH
, and