TB28F008S5-100 Intel, TB28F008S5-100 Datasheet - Page 10

• Manufacturer Part Number: TB28F008S5-100
• Manufacturer: Intel

Specifications of TB28F008S5-100

• Cell Type: NOR
• Density: 8Mb
• Access Time (max): 100ns
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 20b
• Operating Supply Voltage (typ): 5V
• Operating Temp Range: -40C to 85C
• Package Type: SOP
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Word Size: 8b
• Number Of Words: 1M
• Mounting: Surface Mount
• Pin Count: 44
• Lead Free Status / Rohs Status: Not Compliant

28F004S5, 28F008S5, 28F016S5
2.1
Depending on the application, the system designer
may choose to make the V
switchable (available only when memory block
erases, programs, or lock-bit configurations are
required) or hardwired to V
accommodates
encourages optimization of the processor-memory
interface.
When V
altered. When high voltage is applied to V
two-step
configuration command sequences provides pro-
tection
functions are disabled when V
the write lockout voltage V
V
additional protection from inadvertent code or data
alteration by gating erase and program operations.
3.0
The local CPU reads and writes flash memory
in-system. All bus cycles to or from the flash
memory conform to standard microprocessor bus
cycles.
3.1
Block information, identifier codes, or status register
can be read independent of the V
can be at either V
The first task is to write the appropriate read-mode
command (Read Array, Read Identifier Codes, or
Read Status Register) to the CUI. Upon initial
device power-up or after exit from deep power-
down mode, the device automatically resets to read
array mode. Four control pins dictate the data flow
in and out of the component: CE#, OE#, WE#, and
RP#. CE# and OE# must be driven active to obtain
data at the outputs. CE# is the device selection
control, and when active enables the selected
memory device. OE# is the data output (DQ
control and when active drives the selected
memory data onto the I/O bus. WE# must be at V
and RP# must be at V
illustrates a read cycle.
10
IL
. The device’s block locking capability provides
BUS OPERATION
PP
from
Data Protection
Read
block
V
PPLK
unwanted
IH
either
erase,
or V
, memory contents cannot be
HH
.
design
IH
LKO
program,
operations.
or V
PPH1/2
CC
or when RP# is at
PP
voltage is below
PP
HH
practice
. The device
power supply
voltage. RP#
. Figure 16
or
All
lock-bit
0
PP
–DQ
, the
write
and
7
IH
)
3.2
With OE# at a logic-high level (V
outputs are disabled. Output pins DQ
placed in a high-impedance state.
3.3
CE# at a logic-high level (V
standby mode which substantially reduces device
power consumption. DQ
in a high-impedance state independent of OE#. If
deselected
lock-bit
functioning and consuming active power until the
operation completes.
3.4
RP# at V
In read mode, RP#-low deselects the memory,
places output drivers in a high-impedance state,
and turns off all internal circuits. RP# must be held
low for time t
return from power-down until initial memory access
outputs are valid. After this wake-up interval,
normal operation is restored. The CUI resets to
read array mode, and the status register is set to
80H.
During
configuration, RP#-low will abort the operation.
RY/BY# remains low until the reset operation is
complete. Memory contents being altered are no
longer valid; the data may be partially erased or
written. Time t
logic-high (V
written.
As with any automated device, it is important to
assert RP# during system reset. When the system
comes out of reset, it expects to read from the flash
memory. Automated flash memories provide status
information when accessed during block erase,
program, or lock-bit configuration modes. If a CPU
reset occurs with no flash memory reset, proper
CPU initialization may not occur because the flash
memory may be providing status information
instead of array data. Intel’s flash memories allow
proper CPU initialization following a system reset
through the use of the RP# input. In this application,
RP# is controlled by the same RESET# signal that
resets the system CPU.
IL
Output Disable
Standby
Deep Power-Down
block
configuration,
initiates the deep power-down mode.
IH
during
) before another command can be
PLPH
PHWL
erase,
. Time t
is required after RP# goes to
block
0
PRELIMINARY
–DQ
the
program,
IH
PHQV
erase,
) places the device in
7
outputs are placed
device
is required after
IH
), the device
program,
or
0
–DQ
continues
lock-bit
7
are
or