TB28F008S5-100 Intel, TB28F008S5-100 Datasheet - Page 13

• Manufacturer Part Number: TB28F008S5-100
• Manufacturer: Intel

Specifications of TB28F008S5-100

• Cell Type: NOR
• Density: 8Mb
• Access Time (max): 100ns
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 20b
• Operating Supply Voltage (typ): 5V
• Operating Temp Range: -40C to 85C
• Package Type: SOP
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Word Size: 8b
• Number Of Words: 1M
• Mounting: Surface Mount
• Pin Count: 44
• Lead Free Status / Rohs Status: Not Compliant

NOTES:
1. Commands other than those shown above are reserved by Intel for future device implementations and should not be used.
2. Bus operations are defined in Table 2.
3. X = Any valid address within the device.
4. SRD = Data read from status register. See Table 6 for a description of the status register bits.
5. Following the Read Identifier Codes command, read operations access manufacturer, device, block lock, and master lock
6. If the block is locked, RP# must be at V
7. Either 40H or 10H are recognized by the WSM as the program setup.
8. If the master lock-bit is set, RP# must be at V
9. If the master lock-bit is set, RP# must be at V
Read Array/Reset
Read Identifier Codes
Read Status Register
Clear Status Register
Block Erase
Program
Block Erase and Program
Suspend
Block Erase and Program
Resume
Set Block Lock-Bit
Set Master Lock-Bit
Clear Block Lock-Bits
IA = Identifier Code Address: see Figure 5.
BA = Address within the block being erased or locked.
PA = Address of memory location to be programmed.
PD = Data to be programmed at location PA. Data is latched on the rising edge of WE# or CE# (whichever goes high first).
ID = Data read from identifier codes.
codes. See Section 4.2 for read identifier code data.
program to a locked block while RP# is V
master lock-bit is not set, a block lock-bit can be set while RP# is V
clears all block lock-bits. If the master lock-bit is not set, the Clear Block Lock-Bits command can be done while RP# is V
PRELIMINARY
Command
Bus Cycles
Req’d.
Table 3. Command Definitions
HH
1
2
1
2
2
1
2
2
2
1
IH
2
to enable block erase or program operations. Attempts to issue a block erase or
will fail.
HH
HH
to set a block lock-bit. RP# must be at V
to clear block lock-bits. The clear block lock-bits operation simultaneously
Notes Oper
6,7
5
6
6
8
8
9
6
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
First Bus Cycle
IH
(2)
.
Addr
BA
PA
BA
X
X
X
X
X
X
X
X
(1)
(3)
28F004S5, 28F008S5, 28F016S5
Data
FFH
D0H
90H
70H
50H
20H
40H
10H
B0H
60H
60H
60H
or
(4)
HH
to set the master lock-bit. If the
Oper
Read
Read
Write
Write
Write
Write
Write
Second Bus Cycle
(2)
Addr
BA
PA
BA
IA
X
X
X
(3)
Data
SRD
D0H
D0H
01H
F1H
PD
ID
(4)
13
IH
.