TB28F008S5-100 Intel, TB28F008S5-100 Datasheet - Page 29

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TB28F008S5-100

Manufacturer Part Number
TB28F008S5-100
Description
Manufacturer
Intel
Datasheet

Specifications of TB28F008S5-100

Cell Type
NOR
Density
8Mb
Access Time (max)
100ns
Interface Type
Parallel
Boot Type
Not Required
Address Bus
20b
Operating Supply Voltage (typ)
5V
Operating Temp Range
-40C to 85C
Package Type
SOP
Sync/async
Asynchronous
Operating Temperature Classification
Industrial
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Word Size
8b
Number Of Words
1M
Mounting
Surface Mount
Pin Count
44
Lead Free Status / Rohs Status
Not Compliant
AC test inputs are driven at 3.0 V for a Logic "1" and 0.0 V for a Logic "0." Input timing begins, and output timing ends, at 1.5 V.
Input rise and fall times (10% to 90%) <10 ns.
AC test inputs are driven at V
(2.0 V
NOTE:
C
L
includes Jig Capacitance
PRELIMINARY
Figure 14. Transient Equivalent Testing
TTL
DEVICE
) and V
UNDER
TEST
Figure 13. Transient Input/Output Reference Waveform for V
Figure 12. Transient Input/Output Reference Waveform for V
IL
(0.8 V
0.45
0.0
3.0
2.4
Load Circuit
TTL
). Output timing ends at V
OH
INPUT
(2.4 V
INPUT
1.3V
R
TTL
C
1N914
L
L
= 3.3 K
(High Speed Testing Configuration)
) for a Logic "1" and V
(Standard Testing Configuration)
1.5
2.0
0.8
OUT
IH
and V
TEST POINTS
TEST POINTS
IL
. Input rise and fall times (10% to 90%) <10 ns.
OL
(0.45 V
V
V
Test Configuration Capacitance Loading Value
CC
CC
= 5.0 V
= 5.0 V
TTL
Test Configuration
) for a Logic "0." Input timing begins at V
28F004S5, 28F008S5, 28F016S5
5%
10%
1.5
2.0
0.8
CC
CC
OUTPUT
OUTPUT
= 5.0 V
= 5.0 V ± 5%
10%
C
L
100
30
(pF)
IH
29

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