CY7C057V-20AC Cypress Semiconductor Corp, CY7C057V-20AC Datasheet - Page 19

• Manufacturer Part Number: CY7C057V-20AC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C057V-20AC

• Density: 1.125Mb
• Access Time (max): 20ns
• Sync/async: Asynchronous
• Architecture: Not Required
• Clock Freq (max): Not RequiredMHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 15b
• Package Type: TQFP
• Operating Temp Range: 0C to 70C
• Number Of Ports: 2
• Supply Current: 340mA
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.465V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Word Size: 36b
• Number Of Words: 32K
• Lead Free Status / Rohs Status: Not Compliant

Document #: 38-06055 Rev. *B
pin will select long-word (36-bit) operation. A logic “1” level
applied to the Bus Match Select (BM) pin will enable either
byte or word bus width operation on the right port I/Os
depending on the logic level applied to the SIZE pin. The level
of Bus Match Select (BM) must be static throughout device
operation.
Normally, the Bus Size Select (SIZE) pin would have no
standard-cycle application when BM = LOW and the device is
in long-word (36-bit) operation. A “special” mode has been
added however to disable ALL right port I/Os while the chip is
active. This I/O disable mode is implemented when SIZE is
forced to a logic “1” while BM is at a logic “0”. It allows the
bus-matched port to support a chip enable “Don’t Care”
semaphore read/write access similar to that provided on the
left port of the device when all Byte Select (B
are deselected.
The Bus Size Select (SIZE) pin selects either a byte or word
data arrangement on the right port when the Bus Match Select
(BM) pin is HIGH. A logic “1” on the SIZE pin when the BM pin
is HIGH selects a byte bus (9-bit) data arrangement). A logic
“0” on the SIZE pin when the BM pin is HIGH selects a word
bus (18-bit) data arrangement. The level of the Bus Size Select
(SIZE) must also be static throughout normal device operation.
Long-Word (36-bit) Operation
Bus Match Select (BM) and Bus Size Select (SIZE) set to a
logic “0” will enable standard cycle long-word (36-bit)
operation. In this mode, the right port’s I/O operates essentially
in an identical fashion as does the left port of the dual-port
SRAM. However no Byte Select control is available. All 36 bits
of the long-word are shifted into and out of the right port’s I/O
buffer stages. All read and write timing parameters may be
identical with respect to the two data ports. When the right port
is configured for a long-word size, Word Address (WA), and
Byte Address (BA) pins have no application and their inputs
are “Don’t Care”
Note:
52. Even though a logic level applied to a “Don’t Care” input will not change the logical operation of the dual-port, inputs that are temporarily a “Don’t Care” (along
with unused inputs) must not be allowed to float. They must be forced either HIGH or LOW.
[52]
for the external user.
0–3
) control inputs
Word (18-bit) Operation
Word (18-bit) bus sizing operation is enabled when Bus Match
Select (BM) is set to a logic “1” and the Bus SIze Select (SIZE)
pin is set to a logic “0.” In this mode, 18 bits of data are ported
through I/O
(WA) pin during word bus size operation determines whether
the most-significant or least-significant data bits are ported
through the I/O
select fashion (note that when the right port is configured for
word size operation, the Byte Address pin has no application
and its input is “Don’t Care”
Device operation is accomplished by treating the WA pin as an
additional address input and using standard cycle address and
data setup/hold times. When transferring data in word (18-bit)
bus match format, the unused I/O
three-stated.
Byte (9-bit) Operation
Byte (9-bit) bus sizing operation is enabled when Bus Match
Select (BM) is set to a logic “1” and the Bus Size Select (SIZE)
pin is set to a logic “1.” In this mode, data is ported through
I/O
group is selected according to the levels applied to the Word
Address (WA) and Byte Address (BA) input pins.
Device operation is accomplished by treating the Word
Address (WA) pin and the Byte Address (BA) pins as
additional address inputs having standard cycle address and
data set-up/hold times. When transferring data in byte (9-bit)
bus match format, the unused I/O
0R–8R
I/O
I/O
I/O
I/O
27R–35R
18R–26R
I/Os
9R–17R
0R–8R
in four groups of 9-bit bytes. A particular 9-bit byte
0R–17R
0R–17R
. The level applied to the Word Address
Upper-MSB
Lower-MSB
Upper-MSB
Lower-MSB
Rank
pins in an Upper Word/Lower Word
[52]
).
9R–35R
pins are three-stated.
WA
1
1
0
0
CY7C056V
CY7C057V
18R–35R
Page 19 of 23
pins are
BA
1
0
1
0
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