CY7C1380CV25-167AC Cypress Semiconductor Corp, CY7C1380CV25-167AC Datasheet
CY7C1380CV25-167AC
Specifications of CY7C1380CV25-167AC
Related parts for CY7C1380CV25-167AC
CY7C1380CV25-167AC Summary of contents
Page 1
... Write cycles can be one to two or four bytes wide as controlled by the byte write control inputs. GW when active LOW causes all bytes to be written. The CY7C1380CV25/CY7C1382CV25 operates from a +2.5V core power supply. All outputs also operate with a +2.5 supply. All inputs and outputs are JEDEC-standard JESD8-5- compatible ...
Page 2
... Logic Block Diagram – CY7C1380CV25 (512K x 36) A0, A1, A ADDRESS REGISTER MODE ADV CLK ADSC ADSP DQ DQP BYTE BW D WRITE REGISTER DQ DQP BYTE BW C WRITE REGISTER DQ DQP BYTE BW B WRITE REGISTER DQ DQP BYTE A WRITE REGISTER BWE GW ENABLE CE 1 REGISTER SLEEP ZZ CONTROL 2 Logic Block Diagram – CY7C1382CV25 (1M x 18) ...
Page 3
... TQFP Pinout 80 DQP DDQ 4 DDQ SSQ 5 SSQ SSQ 10 SSQ DDQ 11 DDQ CY7C1382CV25 DDQ 20 DDQ SSQ 21 SSQ DQP SSQ 26 SSQ DDQ 27 DDQ DQP CY7C1380CV25 CY7C1382CV25 DDQ 76 V SSQ DQP SSQ 70 V DDQ ( DDQ V 60 SSQ SSQ V 54 DDQ Page [+] Feedback ...
Page 4
... Pin Configurations (continued DDQ DDQ DDQ DDQ DDQ DDQ DDQ DDQ DDQ 72M U V DDQ Document #: 38-05240 Rev. *C 119-ball BGA (1 Chip Enable with JTAG) CY7C1380CV25 (512K x 36 ADSP A A ADSC DQP ADV CLK BWE DQP MODE 72M TMS TDI TCK TDO ...
Page 5
... D D DDQ DDQ N DQP DDQ 72M A R MODE NC / 36M 288M CE2 DDQ DDQ DDQ DDQ DDQ DDQ DDQ DDQ DDQ N DQP DDQ 72M A R MODE NC / 36M A Document #: 38-05240 Rev. *C 165-ball fBGA CY7C1380CV25 (512K x 36 BWE CLK TDI A1 TDO A A0 TCK A TMS ...
Page 6
... CY7C1380CV25–Pin Definitions Name TQFP BGA 37,36,32, P4,N4 33,34,35, A2,B2, 42,43,44,45, C2,R2, 46,47,48, A3,B3,C3, 49,50,81, T3,T4,A5,B5, 82,99,100 C5, T5,A6,B6,C6,R6 93,94,95, L5,G5 G3, BWE CLK [ [ ADV 84 A4 ADSP Document #: 38-05240 Rev. *C fBGA I/O R6,P6,A2, Input- Address Inputs used to select one of the A10,B2, Synchronous address locations. Sampled at the rising edge ...
Page 7
... CY7C1380CV25–Pin Definitions Name TQFP BGA B4 85 ADSC 52,53,56, K6,L6, DQs, 57,58,59, M6,N6, DQPs 62,63,68, K7,L7, 69,72,73, N7,P7, 74,75,78, E6,F6, 79,2,3,6,7,8,9, G6,H6, 12,13,18,19,22 D7,E7, , G7,H7, 23,24,25, D1,E1, 28,29,51, G1,H1, 80,1,30 E2,F2, G2,H2, K1,L1, N1,P1, K2,L2, M2,N2, P6,D6, D2,P2 V 15,41,65, J2,C4,J4,R4 17,40,67, ...
Page 8
... CY7C1380CV25–Pin Definitions Name TQFP BGA V 4,11,20,27,54, A1,F1,J1,M1,U1, DDQ 61,70, A7,F7,J7,M7,U7 77 MODE 31 R3 TDO - U5 TDI - U3 TMS - U2 TCK - U4 NC 14,16,66, B1,C1, 39,38 R1,T1,T2,J3, D4, L4,J5,R5,6T, 6U, B7,C7, R7 CY7C1382CV25–Pin Definitions Name TQFP BGA 37,36,32, P4,N4 33,34,35, A2,B2, 42,43,44, C2,R2, 45,46,47, T2,A3, 48,49,50, B3,C3, 80,81,82, ...
Page 9
... CLK, active LOW. When asserted LOW, addresses presented to the device are captured in the address registers. A1: A0 are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. CY7C1380CV25 CY7C1382CV25 Description X and CE to select/deselect the ...
Page 10
... Serial data-In to the JTAG circuit. Sampled input on the rising edge of TCK. If the JTAG feature Synchronous is not being utilized, this pin can be left floating or connected to V This pin is not available on TQFP packages. CY7C1380CV25 CY7C1382CV25 Description are X or left floating selects interleaved burst through a pull up resistor. ...
Page 11
... DQs inputs is written into the corre- sponding address location in the memory array HIGH, then the Write operation is controlled by BWE and BW signals. The CY7C1380CV25/CY7C1382CV25 provides Byte Write capability that is described in the Write Cycle Descrip- tions table. Asserting the Byte Write Enable input (BWE) with the selected Byte Write (BW only the desired bytes ...
Page 12
... Write mechanism has been provided to simplify the Write operations. Because the CY7C1380CV25/CY7C1382CV25 is a common I/O device, the Output Enable (OE) must be deserted HIGH before presenting data to the DQs inputs. Doing so will three-state the output drivers safety precaution, DQs are automatically three-stated whenever a Write cycle is detected, regardless of the state of OE ...
Page 13
... READ Cycle, Suspend Burst Current READ Cycle, Suspend Burst Current READ Cycle, Suspend Burst Current WRITE Cycle,Suspend Burst Current WRITE Cycle,Suspend Burst Current Truth Table for Read/Write [5] Function (CY7C1380CV25) Read Read Write Byte A – (DQ and DQP ) A A Write Byte B – (DQ and DQP ) B ...
Page 14
... TAPs. The TAP operates using JEDEC-standard 2.5V I/O logic levels. The CY7C1380CV25/CY7C1382CV25 contains a TAP controller, instruction register, boundary scan register, bypass register, and ID register. Disabling the JTAG Feature It is possible to operate the SRAM without using the JTAG feature ...
Page 15
... The TAP controller used in this SRAM is not fully compliant to the 1149.1 convention because some of the mandatory 1149.1 instructions are not fully implemented. The TAP controller cannot be used to load address data or control signals into the SRAM and cannot preload the I/O CY7C1380CV25 CY7C1382CV25 Page [+] Feedback ...
Page 16
... TDI and TDO balls. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions. CY7C1380CV25 CY7C1382CV25 t CH). Page [+] Feedback ...
Page 17
... CH refer to the setup and hold time requirements of latching data from the boundary scan register. 10. Test conditions are specified using the load in TAP AC test Conditions. t Document #: 38-05240 Rev CYC TL t TMSS t TMSH t TDIS t TDIH DON’T CARE UNDEFINED [9, 10] Over the operating Range Description /t = 1ns CY7C1380CV25 CY7C1382CV25 TDOV t TDOX Min. Max. Unit 100 ns 10 MHz ...
Page 18
... Reserved for internal use. 000000 000000 Defines memory type and architecture. 100101 010101 Defines width and density. 00000110100 00000110100 Allows unique identification of SRAM vendor Indicates the presence register. Bit Size (x18 Description CY7C1380CV25 CY7C1382CV25 1.25V 20pF O Min. Max. Unit 2.0 V 2.1 V 0.4 V 0 ...
Page 19
... Places the bypass register between TDI and TDO. This operation does not affect SRAM operations. 119-Ball BGA Boundary Scan Order CY7C1380CV25 (512K x 36) Bit# Ball Document #: 38-05240 Rev. *C CY7C1380CV25 CY7C1382CV25 Description Bit# Ball Not Bonded (Preset to1 Internal 68 L3 Page [+] Feedback ...
Page 20
... CY7C1382CV25 (1M x 18) (continued) Bit CY7C1380CV25 CY7C1382CV25 Internal Ball Not Bonded (Preset to 0) Not Bonded (Preset to 0) Not Bonded (Preset to 0) Not Bonded (Preset Not Bonded (Preset Not Bonded (Preset to 0) Not Bonded (Preset to 0) Not Bonded (Preset to 0) Not Bonded (Preset to 0) ...
Page 21
... A10 45 C11 46 E10 47 F10 48 G10 49 D10 50 D11 51 E11 52 F11 53 G11 54 H11 55 J10 56 K10 57 L10 58 M10 59 J11 60 K11 61 L11 62 M11 63 N11 64 R11 65 R10 CY7C1380CV25 (512K x 36) (continued) Ball ID Bit P10 P11 72 CY7C1382CV25 (1M x 18) Ball ID Bit CY7C1380CV25 CY7C1382CV25 Ball Not Bonded (Preset to1) ...
Page 22
... M10 R11 65 R10 P10 P11 72 CY7C1380CV25 CY7C1382CV25 Not Bonded (Preset to 0) Not Bonded (Preset to 0) Not Bonded (Preset to 0) Not Bonded (Preset Not Bonded (Preset Not Bonded (Preset to 0) Not Bonded (Preset to 0) Not Bonded (Preset to 0) Not Bonded (Preset to 0) ...
Page 23
... Max, Device Deselected, All speeds DD ≥ V ≤ /2), undershoot: V (AC) > -2V (Pulse width less than t CYC IL (min.) within 200ms. During this time V < V and CY7C1380CV25 CY7C1382CV25 + 0.5V DD Ambient Temperature DDQ 0°C to +70°C 2.5V – 5%/+5% 2.5V – Min. Max. 2.375 2.625 2.375 ...
Page 24
... V and t is less than t to eliminate bus contention between SRAMs when sharing the same OELZ CHZ CLZ CY7C1380CV25 CY7C1382CV25 BGA fBGA Package Package Unit °C °C ...
Page 25
... CY7C1380CV25 CY7C1382CV25 133 MHz Unit 1.5 ns 1.5 ns 1.5 ns 1.5 ns 1.5 ns 1.5 ns 0.5 ns 0.5 ns 0.5 ns 0 ...
Page 26
... OEV OEHZ t OELZ t DOH Q(A2 BURST READ DON’T CARE UNDEFINED is HIGH and CE is LOW. When CE is HIGH LOW. X CY7C1380CV25 CY7C1382CV25 A3 Burst continued with new base address Deselect cycle t CHZ Q( Q(A2) Q( Burst wraps around to its initial state is HIGH LOW HIGH. 1 ...
Page 27
... OEHZ Data Out (Q) BURST READ Single WRITE Document #: 38-05240 Rev WES t WEH ADV suspends burst D(A2 BURST WRITE DON’T CARE UNDEFINED CY7C1380CV25 CY7C1382CV25 ADSC extends burst t ADS t ADH A3 t WES t WEH t t ADVH ADVS D( D(A3 Extended BURST WRITE ...
Page 28
... The data bus (Q) remains in high-Z following a WRITE cycle, unless a new read access is initiated by ADSP or ADSC . 24 HIGH. Document #: 38-05240 Rev WES t WEH OELZ D(A3) Q(A4) Q(A4+1) Q(A4+2) Single WRITE BURST READ DON’T CARE UNDEFINED t ZZREC t RZZI DESELECT or READ Only High-Z DON’T CARE CY7C1380CV25 CY7C1382CV25 A5 A6 D(A5) D(A6) Q(A4+3) Back-to-Back WRITEs Page [+] Feedback ...
Page 29
... CY7C1380CV25-225BZC CY7C1382CV25-225BZC 200 CY7C1380CV25-200AC CY7C1382CV25-200AC CY7C1380CV25-200BGC CY7C1382CV25-200BGC CY7C1380CV25-200BZC CY7C1382CV25-200BZC 167 CY7C1380CV25-167AC CY7C1382CV25-167AC CY7C1380CV25-167BGC CY7C1382CV25-167BGC CY7C1380CV25-167BZC CY7C1382CV25-167BZC 133 CY7C1380CV25-133AC Notes: 25. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device. 26. DQs are in high-Z when exiting ZZ sleep mode. ...
Page 30
... MAX. 0.60±0.15 0.20 MIN. 1.00 REF. A DETAIL Document #: 38-05240 Rev. *C DIMENSIONS ARE IN MILLIMETERS 0.30±0.08 0.65 12°±1° TYP. (8X STAND-OFF 0.05 MIN. SEATING PLANE 0.15 MAX. CY7C1380CV25 CY7C1382CV25 1.40±0.05 A SEE DETAIL 0.20 MAX. 1.60 MAX. 51-85050-*A Page [+] Feedback ...
Page 31
... Package Diagrams (continued) Document #: 38-05240 Rev. *C 119-Lead PBGA ( 2.4 mm) BG119 CY7C1380CV25 CY7C1382CV25 51-85115-*B Page [+] Feedback ...
Page 32
... The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. 165-Ball FBGA ( 1.2 mm) BB165A CY7C1380CV25 CY7C1382CV25 51-85122-*C ...
Page 33
... Document History Page Document Title: CY7C1380CV25/CY7C1382CV25 18-Mbit (512K x 36/1M x 18) Pipelined SRAM Document Number: 38-05240 REV. ECN NO. Issue Date ** 116280 08/29/02 *A 121543 11/21/02 *B 206081 See ECN *C 230388 See ECN Document #: 38-05240 Rev. *C Orig. of Change Description of Change SKX New Data Sheet DSG Updated package diagrams 51-85115 (BG119) to rev ...