CY7C1380CV25-167AC Cypress Semiconductor Corp, CY7C1380CV25-167AC Datasheet - Page 11

• Manufacturer Part Number: CY7C1380CV25-167AC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1380CV25-167AC

• Density: 18Mb
• Access Time (max): 3.4ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 166MHz
• Operating Supply Voltage (typ): 2.5V
• Address Bus: 19b
• Package Type: TQFP
• Operating Temp Range: 0C to 70C
• Number Of Ports: 4
• Supply Current: 275mA
• Operating Supply Voltage (min): 2.375V
• Operating Supply Voltage (max): 2.625V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Word Size: 36b
• Number Of Words: 512K
• Lead Free Status / Rohs Status: Not Compliant

Document #: 38-05240 Rev. *C
CY7C1382CV25–Pin Definitions
Functional Overview
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock.
Maximum access delay from the clock rise (t
(200-MHz device).
The CY7C1380CV25/CY7C1382CV25 supports secondary
cache in systems utilizing either a linear or interleaved burst
sequence. The interleaved burst order supports Pentium and
i486 processors. The linear burst sequence is suited for
processors that utilize a linear burst sequence. The burst order
is user selectable, and is determined by sampling the MODE
input. Accesses can be initiated with either the Processor
Address Strobe (ADSP) or the Controller Address Strobe
(ADSC). Address advancement through the burst sequence is
controlled by the ADV input. A two-bit on-chip wraparound
burst counter captures the first address in a burst sequence
and automatically increments the address for the rest of the
burst access.
Byte Write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BW
Enable (GW) overrides all Byte Write inputs and writes data to
all four bytes. All writes are simplified with on-chip
synchronous self-timed Write circuitry.
Three synchronous Chip Selects (CE
asynchronous Output Enable (OE) provide for easy bank
selection and output three-state control. ADSP is ignored if
CE
Single Read Accesses
This access is initiated when the following conditions are
satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2)
CE
signals (GW, BWE) are all deserted HIGH. ADSP is ignored if
TMS
TCK
NC
Name
1
1
, CE
is HIGH.
2
, CE
1,2,3,6,7,
14,16,25,
28,29,30,
51,52,53,
56,57,66,
75,78,79,
3
38,39,
TQFP
95,96
are all asserted active, and (3) the Write
-
-
N2,L7,P1,P6,
K6,L4,L2,L7,
J3,J5,K1,
T1,T4,U6
C1,C7,
D2,D4,
G6,H7,
R5,R7,
B1,B7,
D7,E1,
E6,H2,
F2,G1,
BGA
M6,
R1,
U2
U4
X
) inputs. A Global Write
1
, CE
(continued)
G10,H1,H3,H9,H10,
C1,C2,C10,D1,D10,
K11,L2,L1,M2,M11,
2
, CE
CO
N2,N7,N10,
E1,E10,F1,
N11,P1,A1,
A5,B1,B4,
F10,G1,
J2,J11,
) is 3.0ns
3
P2,R2
fBGA
) and an
B11,
K2,
N5,
R5
R7
CE
is stored into the address advancement logic and the Address
Register while being presented to the memory array. The
corresponding data is allowed to propagate to the input of the
Output Registers. At the rising edge of the next clock the data
is allowed to propagate through the output register and onto
the data bus within 3.0 ns (200-MHz device) if OE is active
LOW. The only exception occurs when the SRAM is emerging
from a deselected state to a selected state, its outputs are
always three-stated during the first cycle of the access. After
the first cycle of the access, the outputs are controlled by the
OE signal. Consecutive single Read cycles are supported.
Once the SRAM is deselected at clock rise by the chip select
and either ADSP or ADSC signals, its output will three-state
immediately.
Single Write Accesses Initiated by ADSP
This access is initiated when both of the following conditions
are satisfied at clock rise: (1) ADSP is asserted LOW, and
(2) CE
presented to A is loaded into the address register and the
address advancement logic while being delivered to the
memory array. The Write signals (GW, BWE, and BW
ADV inputs are ignored during this first cycle.
ADSP-triggered Write accesses require two clock cycles to
complete. If GW is asserted LOW on the second clock rise, the
data presented to the DQs inputs is written into the corre-
sponding address location in the memory array. If GW is HIGH,
then the Write operation is controlled by BWE and BW
signals. The CY7C1380CV25/CY7C1382CV25 provides Byte
Write capability that is described in the Write Cycle Descrip-
tions table. Asserting the Byte Write Enable input (BWE) with
the selected Byte Write (BW
only the desired bytes. Bytes not selected during a Byte Write
operation will remain unaltered. A synchronous self-timed
Synchronous
JTAG-Clock Clock input to the JTAG circuitry. If the JTAG
JTAG serial
1
input
is HIGH. The address presented to the address inputs (A)
I/O
1
-
, CE
2
, CE
Serial data-In to the JTAG circuit. Sampled
on the rising edge of TCK. If the JTAG feature
is not being utilized, this pin can be discon-
nected or connected to V
available on TQFP packages.
feature is not being utilized, this pin must be
connected to V
TQFP packages.
No Connects. Not internally connected to the
die.
3
are all asserted active. The address
X
SS
) input, will selectively write to
Description
. This pin is not available on
CY7C1380CV25
CY7C1382CV25
DD
. This pin is not
Page 11 of 33
X
) and
X
[+] Feedback