CY7C1386B-133AC Cypress Semiconductor Corp, CY7C1386B-133AC Datasheet

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... Read cycle. This device also incorporates pipelined enable circuit for easy depth expansion without penalizing system performance. The CY7C1386B and CY7C1387B are both double-cycle SRAMs integrate deselect parts. All inputs and outputs of the CY7C1386B and the CY7C1387B are JEDEC-standard JESD8-5-compatible. 200 MHz 167 MHz 3 3 ...

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... Logic Block Diagram CY7C1386B — 512K × 36 CLK ADV ADSC ADSP A [18: BWE CY7C1387B — 1M × 18 Logic Block Diagram CLK ADV ADSC ADSP A [19: BWE Document #: 38-05195 Rev. ** MODE ( [1;0] Q BURST 0 COUNTER CE Q CLR ADDRESS CE REGISTER BYTEWRITE REGISTERS BYTEWRITE REGISTERS BYTEWRITE ...

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... DDQ DDQ SSQ SSQ DQb DQa 59 22 DQb DQa 58 23 DPb DQa DQa SSQ SSQ DDQ DDQ DQa DQa 52 29 DQPa CY7C1386B CY7C1387B DDQ 76 V SSQ DPa DQa 73 DQa SSQ V 70 DDQ DQa 69 DQa (1M × 18 DQa 63 DQa DDQ V 60 SSQ DQa ...

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... V M DDQ N DQd P DQd DDQ DDQ DQb DDQ DQb J V DDQ DQb M V DDQ N DQb 64M DDQ Document #: 38-05195 Rev. ** 119-Ball BGA — Top View CY7C1386B (512K × 36 ADSP ADSC DQPc DQc V CE1 DQc DQc BWc ADV BWb DQc DQd V CLK V ...

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... DQb V DDQ G NC DQb V DDQ DQb NC V DDQ K DQb NC V DDQ L DQb NC V DDQ M DQb NC V DDQ N DPb NC V DDQ P NC 64M R MODE 32M Document #: 38-05195 Rev. ** 165-Ball Bump FBGA CY7C1386B (512K × 36) — 11 × 15 FBGA BWc BWb BWd BWa CLK ...

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... A rise of the read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQx and DPx are placed in a three-state condition.DQ a,b,c and d are 8 bits wide. DP a,b,c and d are 1 bit wide. CY7C1386B CY7C1387B ...

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... Power supply for the I/O circuitry. Should be connected to a 2.5V – 3.3V –5% +10% power supply (see page 20). Ground for the I/O circuitry. Should be connected to ground of the system. No connects. Pins are not internally connected. No connects. Reserved for address expansion. Pins are not internally connected. CY7C1386B CY7C1387B Page ...

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... Bytes not selected during a byte Write operation will remain unaltered. A synchronous 1 self-timed Write mechanism has been provided to simplify Write operations. Because the CY7C1386B/CY7C1387B is a common I/O device, the OE must be deasserted HIGH before presenting data to the DQ drivers safety precaution, DQ three-stated whenever a write cycle is detected, regardless of the state of OE ...

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... ZZ Mode Electrical Characteristics Parameter Description Fourth Address I DDZZ A [1:0] [1: ZZS ZZREC 01 10 CY7C1386B CY7C1387B after the ZZ input returns ZZREC Test Conditions Min. Max. Unit Sleep mode ZZ > V – 0.2V DD standby current Device ZZ > V – 0.2V DD operation recovery ZZ < 0.2V 2t CYC ...

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... Document #: 38-05195 Rev ADSP CY7C1386B CY7C1387B ADSC ADV Hi-Z Read Hi-Z Read Read Hi-Z Read Read Hi-Z Read Read Hi-Z Read Read Hi-Z Write Hi-Z Write Hi-Z Write Hi-Z Write Hi-Z Write Hi-Z Write Hi-Z Write Hi Page Write ...

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... OE is asynchronous and is not sampled with the clock rise masked internally during Write cycles. During a Read cycle DQ = High-Z when OE is inactive or when the device is deselected, and DQ = data when OE is active. Document #: 38-05195 Rev BWE BWd BWE Writes may occur only on subsequent clocks after x CY7C1386B CY7C1387B BWc BWb BWa BWb BWa Page ...

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... IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C1386B/CY7C1387B incorporates a serial boundary scan Test Access Port (TAP) in the FBGA package only. The TQFP package does not offer this functionality. This port operates in accordance with IEEE Standard 1149.1-1900, but does not have the set of functions required for full 1149.1 compliance ...

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... TDI and TDO pins. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions. CY7C1386B CY7C1387B Page ...

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... RESET 1 TEST-LOGIC/ 0 IDLE Note: 8. The 0/1 next to each state represents the value at TMS at the rising edge of TCK. Document #: 38-05195 Rev SELECT DR-SCAN 0 1 CAPTURE-DR 0 SHIFT- EXIT1- PAUSE- EXIT2-DR 1 UPDATE- CY7C1386B CY7C1387B 1 SELECT IR-SCAN 0 1 CAPTURE-DR 0 SHIFT- EXIT1- PAUSE- EXIT2-IR 1 UPDATE- Page ...

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... TAP Controller [9, 10] Over the Operating Range Test Conditions 100 8 100 A OL GND DDQ /2, Undershoot:V (AC)<0.5V for t<t /2, Power-up TCYC CY7C1386B CY7C1387B 0 Selection Circuitry Min. Max. 2 0.2 DD 0.4 0.2 1.7 V 0.3 DD 0.5 0 <2.6V and V <2.4V and V <1.4V for t<200 ms. ...

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... CS CH 12. Test conditions are specified using the load in TAP AC test conditions. TR/ ns. Document #: 38-05195 Rev. ** [11 ,12] Over the Operating Range Description CY7C1386B CY7C1387B Min. Max. Unit 100 ns 10 MHz ...

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... TAP Timing and Test Conditions 1.25V 50 TDO GND (a) Test Clock TCK Test Mode Select TMS Test Data-In TDI Test Data-Out TDO Document #: 38-05195 Rev. ** ALL INPUT PULSES 3.3V 1.50V TCYC t TMSS t TMSH t TDIS t TDIH t t TDOX TDOV CY7C1386B CY7C1387B Page ...

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... Do Not Use. This instruction is reserved for future use. Do Not Use: This instruction is reserved for future use. Places the bypass register between TDI and TDO. This operation does not affect SRAM operation. CY7C1386B CY7C1387B Description Reserved for version number. Defines depth of SRAM. 512K or 1M. ...

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... DQd 1L 21 ADV# DQd 2M 22 ADSP# DQd 1N 23 ADSC# DQd 2P 24 OE# DQd 1K 25 BWE# DQd 2L 26 GW# DQd 2N 27 CLK DQd MODE 3R 29 BWa BWb CE DQb CY7C1386B CY7C1387B Bump Signal Bump ID Bit # Name DQb DQb DQb DQb DQb DQb DQb DQb MODE ...

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... DDQ 6.7-ns cycle, 150 MHz 1/t MAX CYC 7.5-ns cycle, 133 MHz Max Device All Speeds DD Deselected CY7C1386B CY7C1387B Ambient [14.] Temp DDQ 0°C to +70°C 3.3V 2.5V –5% –5%/+10% 3.3V + 10% -40°C to +85°C Min. Max. 3.135 3.63 2.375 3.63 2.375 ...

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... Input waveform should have a slew rate of 1 V/ns. Document #: 38-05195 Rev. ** Test Conditions T 25° MHz 3.3 DDQ [16 317 V DDQ OUTPUT 351 INCLUDING JIG AND SCOPE (b) Test Conditions CY7C1386B CY7C1387B Max [16] ALL INPUT PULSES 3.0V 90% 90% 10% GND 1 V/ns ( (Junction to Ambient) (Junction to Case) 41.54 6.33 44.51 2 ...

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... EOLZ CHZ CLZ CY7C1386B CY7C1387B –167 –150 –133 Max. Min. Max. Min. Max. 6.7 7.5 2.3 2.5 2.3 2.5 1.5 1.5 0.5 0.5 3.4 3 ...

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... WE is the combination of BWE, BWx, and GW to define a Write cycle (see Write cycle descriptions table). 21. WDx stands for Write Data to Address X. Document #: 38-05195 Rev. ** Burst Write ADSP ignored with CE inactive CL 1 WD2 masks ADSP Undefined = Don’t Care CY7C1386B CY7C1387B Pipelined Write Unselected ADSC initiated Write WD3 Unselected with CE 2 High Page ...

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... RDx stands for Read Data from Address X. Document #: 38-05195 Rev. ** Burst Read ADSP ignored with Suspend Burst ADH masks ADSP OEHZ t DOH CLZ = Don’t Care = Undefined CY7C1386B CY7C1387B Unselected Pipelined Read inactive 1 ADSC initiated Read RD3 Unselected with CE 2 Double-Cycle Deselect Page CHZ ...

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... EOLZ Data In/Out 1a Out t CO Document #: 38-05195 Rev. ** Single Write Burst Read ADSP ignored with ADH RD3 masks ADSP 1 t EOHZ Out In = Don’t Care = Undefined CY7C1386B CY7C1387B Unselected Pipelined Read inactive Double-Cycle DH DOH Deselect Out Out Out Out t CHZ Page ...

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... CE is the combination of CE and CE . All chip selects need to be active in order to select the device Document #: 38-05195 Rev CYC CH WD1 t ADH t CEH t WES ADSP ignored with CE HIGH Out Out = Don’t Care = Undefined CY7C1386B CY7C1387B CL WD2 WD3 WD4 t WEH D( DOH t CHZ Page ...

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... Note: 25. Device must be deselected when entering ZZ mode. See Cycle Descriptions Table for all possible signal conditions to deselect the device. 26. I/Os are in three-state when exiting ZZ sleep mode. Document #: 38-05195 Rev EOV t EOHZ Three-State t EOLZ t ZZS I (active DDZZ Three-state CY7C1386B CY7C1387B t ZZREC Page ...

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... Ordering Information Speed (MHz) Ordering Code 200 CY7C1386B-200AC 167 CY7C1386B-167AC 150 CY7C1386B-150AC 133 CY7C1386B-133AC 200 CY7C1387B-200AC 167 –167AC 150 –150AC 133 –133AC 200 CY7C1386B-200BGC 167 CY7C1386B-167BGC 150 CY7C1386B-150BGC 133 CY7C1386B-133BGC 200 CY7C1387B-200BGC 167 –167BGC 150 –150BGC 133 –133BGC 200 CY7C1386B-200BZC 167 ...

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... Package Diagrams 100-Pin Thin Plastic Quad Flatpack (14 × 20 × 1.4 mm) Document #: 38-05195 Rev. ** CY7C1386B CY7C1387B 51-85050-A Page ...

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... Package Diagrams (continued) Document #: 38-05195 Rev. ** 119-Ball BGA (14 × 22 × 2.4 mm) CY7C1386B CY7C1387B Page ...

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... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. 165-Ball FBGA (13 × 15 × 1.2 mm) BB165A CY7C1386B CY7C1387B Page ...

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... Revision History Document Title: CY7C1386B/CY7C1387B 512K x 36/ Pipelined DCD SRAM Document Number:38-05195 ISSUE REV. ECN NO. DATE ** 112030 12/09/01 Document #: 38-05195 Rev. ** ORIG. OF CHANGE DESCRIPTION OF CHANGE DSG Change from Spec number: 38-01117 to 38-05195 CY7C1386B CY7C1387B Page ...