CY7C344-25WMB E2V, CY7C344-25WMB Datasheet - Page 3

• Manufacturer Part Number: CY7C344-25WMB
• Manufacturer: E2V

Specifications of CY7C344-25WMB

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Timing Delays
Timing delays within the CY7C344/CY7C344B may be easily
determined using Warp2 ®, Warp2 Sim™ , or Warp3 ® software
or by the model shown in Figure 1 . The CY7C344/CY7C344B
has fixed internal delays, allowing the user to determine the
worst case timing delays for any design. For complete timing
information, the Warp3 software provides a timing simulator.
Design Recommendations
Operation of the devices described herein with conditions
above those listed under “Absolute Maximum Ratings” may
cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of
this datasheet is not implied. Exposure to absolute maximum
ratings conditions for extended periods of time may affect de-
vice reliability. The CY7C344/CY7C344B contains circuitry to
protect device pins from high-static voltages or electric fields;
however, normal precautions should be taken to avoid applying
any voltage higher than maximum rated voltages.
For proper operation, input and output pins must be con-
strained to the range GND
puts must always be tied to an appropriate logic level (either VCC or
GND). Each set of VCC and GND pins must be connected together
directly at the device. Power supply decoupling capacitors of at least
0.2 F must be connected between VCC and GND. For the most
effective decoupling, each VCC pin should be separately decoupled.
Timing Considerations
Unless otherwise stated, propagation delays do not include
expanders. When using expanders, add the maximum ex-
pander delay t
When calculating synchronous frequencies, use t
are on the input pins. t
pin. If t
in the data-path mode unless 1/(t
S2
INPUT
I/O
is greater than t
EXP
to the overall delay.
I/O DELAY
S2
DELAY
INPUT
I/O
t
t
IN
IO
CO1
should be used if data is applied at an I/O
, 1/t
(VIN or VOUT)
WH
S2
becomes the limiting frequency
+ t
WL
) is less than 1/t
Figure 1. CY7C344/CY7C344B Timing Model
SYSTEM CLOCK DELAYt
VCC. Unused in-
CONTROLDELAY
LOGIC ARRAY
LOGIC ARRAY
EXPANDER
S1
DELAY
DELAY
CLOCK
t
DELAY
t
t
if all inputs
S2
LAC
LAD
EXP
t
IC
.
3
t
t
t
t
CLR
PRE
RSU
RH
ICS
FEEDBACK
When expander logic is used in the data path, add the appro-
priate maximum expander delay, t
1/(t
lowest of these frequencies is the maximum data-path frequency for
the synchronous configuration.
When calculating external asynchronous frequencies, use
t
an I/O pin, t
t
quency in the data-path mode unless 1/(t
1/(t
When expander logic is used in the data path, add the appro-
priate maximum expander delay, t
of 1/(t
The lowest of these frequencies is the maximum data-path frequency
for the asynchronous configuration.
The parameter t
when driving other synchronous logic with positive input hold times,
which is controlled by the same synchronous clock. If t
than the minimum required input hold time of the subsequent syn-
chronous logic, then the devices are guaranteed to function properly
with a common synchronous clock under worst-case environmental
and supply voltage conditions.
The parameter t
vice when driving subsequent registered logic with a positive hold
time and using the same clock as the CY7C344/CY7C344B.In gen-
eral, if t
the subsequent logic (synchronous or asynchronous), then the devic-
es are guaranteed to function properly under worst-case environ-
mental and supply voltage conditions, provided the clock signal
source is the same. This also applies if expander logic is used in the
clock signal path of the driving device, but not for the driven device.
This is due to the expander logic in the second device’s clock signal
path adding an additional delay (t
the preceding device to change prior to the arrival of the clock signal
at the following device’s register.
AH
AS1
DELAY
WH
AS2
) is greater than t
t
FD
if all inputs are on dedicated input pins. If any data is applied to
AWH
+ t
+ t
AOH
REGISTER
WL
AH
+ t
t
t
LATCH
COMB
AS2
t
RD
), 1/t
).
AWL
is greater than the minimum required input hold time of
must be used as the required set-up time. If (t
), 1/t
CO1
OH
AOH
ACO1
ACO1
indicates the system compatibility of this device
, or 1/(t
indicates the system compatibility of this de-
, 1/(t
, or 1/(t
C344–7
EXP
AS2
OUTPUT
DELAY
+ t
EXP
EXP
t
t
t
OD
XZ
ZX
+ t
S1
), causing the output data from
EXP
+ t
EXP
) is the lowest frequency. The
AH
AS1
) becomes the limiting fre-
to t
AWH
to t
) is the lowest frequency.
S1
AS1
. Determine which of
+ t
CY7C344B
. Determine which
OUTPUT
AWL
CY7C344
) is less than
OH
is greater
AS2
+