5962-9201001MXC Cypress Semiconductor Corp, 5962-9201001MXC Datasheet - Page 52

• Manufacturer Part Number: 5962-9201001MXC
• Manufacturer: Cypress Semiconductor Corp

Specifications of 5962-9201001MXC

• Lead Free Status / Rohs Status: Not Compliant

DSCC FORM 2234
APR 97
R/ W
SlZ1, SIZ0
FC2, FC1
HALT
Symbol
DEFENSE SUPPLY CENTER COLUMBUS
MICROCIRCUIT DRAWING
COLUMBUS, OHIO 43216-5000
The local data direction signal is both an input and a rescinding output. This signal is driven while
device is a local bus master to indicate local data direction. As an input, R/ W indicates data direction
for VMEbus master cycles. In this case, WRITE reflects the value of R/ W . An asserted condition
indicates a write operation.
The halt condition indication signal is an input and an open collector output. This signal, HALT along
with RESET , is asserted during reset conditions. An internal, global and system reset causes the
device to assert HALT for a minimum of 200 ms. If the reset condition continues for longer than
200 ms, HALT begins an additional 200 ms timeouts until all reset conditions are cleared. Assertion of
sequence for Motorola 68K processors.
The local data size signals are both inputs and rescinding outputs. As inputs, these signals should
identify the width of the VMEbus data to be transferred. The SIZi signals should not be used to indicate
the physical port size of the slave device (D16 or D32). This is done with the WORD signal. As
outputs, they are driven by the device as local bus master to identify the width of the incoming data.
The local function code signals are both inputs and rescinding outputs. These signals identify the type
of local cycle in progress. As inputs, they should reflect the type of operations in terms of
User/Supervisory Code/Data. They may be connected directly to the Motorola FC2/1 outputs for 68000-
30 processors. For the 68040, FC2/1 inputs may be connected to the TM2/1 outputs, respectively.
Addition qualification may be required for 68040 applications since the 68040 uses previously
reserved/unused function codes.
As outputs, the device drives these signals whenever local bus master to indicate the type of local bus
master to indicate the type of local cycle the device is performing.
HALT for greater than 4 ms by anything other than the device causes the device to assert SYSFAIL .
HALT may be configured to assert during dead-lock conditions along with LBERR to initiate a retry
STANDARD
SIZ1
FC2
FC2
0
0
1
1
0
0
1
1
0
0
1
1
SIZ0
FC1
FC1
TABLE III. Pin description - Continued.
0
1
0
1
0
1
0
1
0
1
0
1
Data Width
Long Word
Byte
Word
3-Byte
Description
User Data
User Program
Supervisory Data
Supervisory Program
Description
Slave Block Transfer
Local DMA
Slave Access
DRAM refresh
Name and function
SIZE
A
REVISION LEVEL
B
SHEET
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