CY25100SCF Cypress Semiconductor Corp, CY25100SCF Datasheet - Page 5

• Manufacturer Part Number: CY25100SCF
• Manufacturer: Cypress Semiconductor Corp
• Type: Programmable PLL Clock Generatorr

Specifications of CY25100SCF

• Number Of Elements: 1
• Supply Current: 35mA
• Pll Input Freq (min): 8MHz
• Pll Input Freq (max): 166MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Package Type: SOIC
• Output Frequency Range: 3 to 200MHz
• Operating Supply Voltage (min): 3.13V
• Operating Supply Voltage (max): 3.45V
• Operating Temperature Classification: Commercial
• Pin Count: 8
• Lead Free Status / Rohs Status: Not Compliant

DC Electrical Characteristics
AC Electrical Characteristics
Document #: 38-07499 Rev. *F
I
I
DC
SR1
SR2
SR3
SR4
T
T
T
t
T
T
t
t
Note
Parameter
VDD
DDS
Parameter
STP
PU1
PU2
2. Jitter is configuration dependent. Actual jitter is dependent on XIN jitter and edge rate, number of active outputs, output frequencies, spread percentage, temperature,
OE1
OE2
CCJ1
CCJ2
CCJ3
and output load.
[2]
[2]
[2]
Supply Current
Standby Current
Output Duty Cycle
Output Duty Cycle
Rising Edge Slew Rate
Falling Edge Slew Rate
Rising Edge Slew Rate
Falling Edge Slew Rate
Cycle-to-Cycle Jitter
SSCLK (Pin 7)
Cycle-to-Cycle Jitter
SSCLK (Pin 7)
Cycle-to-Cycle Jitter
REFCLK (Pin 6)
Power down Time
(pin 4 = PD#)
Output Disable Time
(pin 4 = OE)
Output Enable Time
(pin 4 = OE)
Power Up Time,
Crystal is used
Power Up Time,
Reference clock is used
Description
Description
[1]
(continued)
V
REFCLK = 30 MHz, SSCLK = 66 MHz,
C
V
PD# = 0V (driven reference pulled down)
SSCLK, Measured at V
REFCLK, Measured at V
Duty Cycle of CLKIN = 50% at input bias
SSCLK from 3 to 100 MHz; REFCLK from 3 to
100 MHz. 20%–80% of V
SSCLK from 3 to 100 MHz; REFCLK from 3 to
100 MHz. 80%–20% of V
SSCLK from 100 to 200 MHz; REFCLK from 100
to 166 MHz 20%–80% of V
SSCLK from 100 to 200 MHz; REFCLK from 100
to 166 MHz 80%–20% of V
CLKIN = SSCLK = 166 MHz, 2% spread,
REFCLK off
CLKIN = SSCLK = 66 MHz, 2% spread,
REFCLK off
CLKIN = SSCLK = 33 MHz, 2% spread,
REFCLK off
CLKIN = SSCLK = 166 MHz, 2% spread,
REFCLK on
CLKIN = SSCLK = 66 MHz, 2% spread,
REFCLK on
CLKIN = SSCLK = 33 MHz, 2% spread,
REFCLK on
CLKIN = SSCLK = 166 MHz, 2% spread,
REFCLK on
CLKIN = SSCLK = 66 MHz, 2% spread,
REFCLK on
CLKIN = SSCLK = 33 MHz, 2% spread,
REFCLK on
Time from falling edge on PD# to stopped
outputs (Asynchronous)
Time from falling edge on OE to stopped outputs
(Asynchronous)
Time from rising edge on OE to outputs at a valid
frequency (Asynchronous)
Time from rising edge on PD# to outputs at valid
frequency (Asynchronous)
Time from rising edge on PD# to outputs at valid
frequency (Asynchronous), reference clock at
correct frequency
DD
DD
LOAD
= 3.45V, Fin = 30 MHz,
= 3.45V, Device powered down with
= 15 pF, PD#/OE = SSON# = V
Condition
Condition
DD
DD
DD
DD
/2
DD
DD
/2
DD
Min
Min
0.7
0.7
1.0
1.2
45
40
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Typ
Typ
100
130
100
105
200
100
135
150
150
150
1.1
1.1
1.6
1.6
3.5
25
15
50
50
90
80
2
CY25100
Max
Max
120
130
170
130
140
260
100
130
180
350
350
350
3.6
3.6
4.0
4.0
Page 5 of 13
35
30
55
60
5
3
Unit
Unit
V/ns
V/ns
V/ns
V/ns
mA
μA
ms
ms
ps
ps
ps
ps
ps
ps
ps
ns
ns
ns
ps
ps
%
%
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