CY7C1351F-100BGC Cypress Semiconductor Corp, CY7C1351F-100BGC Datasheet - Page 10

• Manufacturer Part Number: CY7C1351F-100BGC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1351F-100BGC

• Lead Free Status / Rohs Status: Not Compliant

Document #: 38-05210 Rev. *B
Switching Characteristics
t
Clock
t
t
t
Output Times
t
t
t
t
t
t
t
Set-up Times
t
t
t
t
t
t
Hold Times
t
t
t
t
t
t
Shaded areas contain advance information.
Notes:
13. This part has a voltage regulator internally; tpower is the time that the power needs to be supplied above V
14. t
15. At any given voltage and temperature, t
16. This parameter is sampled and not 100% tested.
17. Timing reference level is 1.5V when V
18. Test conditions shown in (a) of AC Test Loads, unless otherwise noted.
POWER
CYC
CH
CL
CDV
DOH
CLZ
CHZ
OEV
OELZ
OEHZ
AS
ALS
WES
CENS
DS
CES
AH
ALH
WEH
CENH
DH
CEH
Parameter
can be initiated.
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve Three-state prior to Low-Z under the same system conditions
CHZ
, t
CLZ
,t
OELZ
, and t
V
Clock Cycle Time
Clock HIGH
Clock LOW
Data Output Valid After CLK Rise
Data Output Hold After CLK Rise
Clock to Low-Z
Clock to High-Z
OE LOW to Output Valid
OE LOW to Output Low-Z
OE HIGH to Output High-Z
Address Set-up Before CLK Rise
ADV/LD Set-up Before CLK Rise
WE, BW
CEN Set-up Before CLK Rise
Data Input Set-up Before CLK Rise
Chip Enable Set-Up Before CLK Rise
Address Hold After CLK Rise
ADV/LD Hold after CLK Rise
WE, BW
CEN Hold After CLK Rise
Data Input Hold After CLK Rise
Chip Enable Hold After CLK Rise
DD
OEHZ
(Typical) to the first Access
are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
[A:D]
[A:D]
Set-Up Before CLK Rise
Hold After CLK Rise
DDQ
[14, 15, 16]
14, 15, 16]
OEHZ
Over the Operating Range
=3.3V and is 1.25V when V
Description
is less than t
[14, 15, 16]
[14, 15, 16]
OELZ
[13]
and t
CHZ
DDQ
is less than t
[17, 18]
= 2.5V.
CLZ
Min. Max. Min. Max. Min. Max. Min. Max.
to eliminate bus contention between SRAMs when sharing the same
7.5
2.5
2.5
2.0
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
133 MHz
1
0
0
6.5
3.5
3.5
3.5
8.5
3.0
3.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
0.5
0.5
0.5
0.5
0.5
0.5
117 MHz
DD
1
0
0
minimum initially before a read or write operation
7.5
3.5
3.5
3.5
4.0
4.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
0.5
0.5
0.5
0.5
0.5
0.5
100 MHz
10
1
0
0
8.0
3.5
3.5
3.5
CY7C1351F
5.0
5.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
0.5
0.5
0.5
0.5
0.5
0.5
15
66 MHz
1
0
0
Page 10 of 15
11.0
5.0
6.0
6.0
Unit
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns