CY7C1354A-166AC Cypress Semiconductor Corp, CY7C1354A-166AC Datasheet - Page 6

• Manufacturer Part Number: CY7C1354A-166AC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1354A-166AC

• Density: 9Mb
• Access Time (max): 3.6ns
• Operating Supply Voltage (typ): 3.3V
• Package Type: TQFP
• Operating Temp Range: 0C to 70C
• Supply Current: 480mA
• Operating Supply Voltage (min): 3.14V
• Operating Supply Voltage (max): 3.47V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Word Size: 36b
• Lead Free Status / Rohs Status: Not Compliant

Document #: 38-05161 Rev. *B
Pin Descriptions—256K × 36
Pin Descriptions—512K × 18
1, 2, 3, 6-9, 12,
51, 52, 53, 56-
14, 15, 16, 41,
26, 40, 55, 60,
32, 33, 34, 35,
44, 45, 46, 47,
48, 49, 50, 80,
81, 82, 83, 99,
68, 69, 72-75,
18, 19, 22-25,
67, 71, 76, 90
54, 61, 70, 77
5, 10, 17, 21,
4, 11, 20, 27,
TQFP Pins
TQFP Pins
256K × 36
512K × 18
59, 62, 63
78, 79, 80
28, 29, 30
65, 66, 91
100
37,
36,
93,
94,
13
38
39
43
42
84
87
6N, 6M, 6L, 7L,
(b) 7H, 6H, 7G,
6G, 6F, 6E, 7E,
2E, 2F, 1G, 2G,
2L, 2M, 1N, 2N,
3D, 5D, 3E, 5E,
5M, 3N, 5N, 3P,
1J, 7J, 1M, 7M,
4A, 1B, 7B, 1C,
2A, 3A, 5A, 6A,
3B, 5B, 6B, 2C,
3C, 5C, 6C, 4G,
(c) 2D, 1D, 1E,
3F, 5F, 3H, 5H,
7C, 4D, 3J, 5J,
1A, 7A, 1F, 7F,
4L, 1R, 7R, 1T,
2R, 6R, 2T, 3T,
(a) 6P, 7P, 7N,
(d) 1K, 2K, 1L,
4C, 2J, 4J, 6J,
PBGA Pins
3K, 5K, 3M,
PBGA Pins
256K × 36
2T, 6T, 6U
512K × 18
7D, 6D,
1H, 2H,
6K, 7K,
4R, 5R
1U, 7U
1P, 2P
5T, 6T
2U
3U
4U
5U
5P
3G
4M
4P
4N
5L
Name
Name
V
TMS
TDO
BWa,
DQa
DQb
DQc
DQd
TCK
V
BWb
CEN
V
Pin
TDI
NC
Pin
A0,
A1,
CCQ
CC
SS
A
(continued)
Synchronous
Synchronous
Synchronous
I/O Supply
Ground
Supply
Output
Output
Input/
Input-
Input-
Input-
Type
Type
Input
–
Synchronous Address Inputs: The address register is triggered by a
combination of the rising edge of CLK, ADV/LD LOW, CEN LOW, and
true chip enables. A0 and A1 are the two least significant bits of the
address field and set the internal burst counter if burst cycle is initiated.
Synchronous Byte Write Enables: Each nine-bit byte has its own
active LOW byte Write enable. On load Write cycles (when WEN and
ADV/LD are sampled LOW), the appropriate byte Write signal (BWx)
must be valid. The byte Write signal must also be valid on each cycle of
a burst Write. Byte Write signals are ignored when WEN is sampled
HIGH. The appropriate byte(s) of data are written into the device two
cycles later. BWa controls DQa pins; BWb controls DQb pins. BWx can
all be tied LOW if always doing Write to the entire 18-bit word.
Synchronous Clock Enable Input: When CEN is sampled HIGH, all
other synchronous inputs, including clock are ignored and outputs
remain unchanged. The effect of CEN sampled HIGH on the device
outputs is as if the LOW-to-HIGH clock transition did not occur. For
normal operation, CEN must be sampled LOW at rising edge of clock.
Data Inputs/Outputs: Both the data input path and data output path are
registered and triggered by the rising edge of CLK. Byte “a” is DQa pins;
Byte “b” is DQb pins; Byte “c” is DQc pins; Byte “d” is DQd pins.
IEEE 1149.1 Test Inputs: LVTTL-level inputs. If Serial Boundary Scan
(JTAG) is not used, these pins can be floating (i.e., No Connect) or be
connected to V
IEEE 1149.1 Test Output: LVTTL-level output. If Serial Boundary Scan
(JTAG) is not used, these pins can be floating (i.e., No Connect).
Power Supply: +3.3V –5% and +5%.
Ground: GND.
Output Buffer Supply: +3.3V –0.165V and +0.165V for 3.3V I/O. +2.5V
–0.125V and +0.4V for 2.5V I/O.
No Connect: These signals are not internally connected. It can be left
floating or be connected to V
CC
.
CY7C1354A/GVT71256ZC36
CY7C1356A/GVT71512ZC18
Pin Description
Pin Description
CC
or to GND.
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