CY7C1354A-166AC Cypress Semiconductor Corp, CY7C1354A-166AC Datasheet - Page 9

• Manufacturer Part Number: CY7C1354A-166AC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1354A-166AC

• Density: 9Mb
• Access Time (max): 3.6ns
• Operating Supply Voltage (typ): 3.3V
• Package Type: TQFP
• Operating Temp Range: 0C to 70C
• Supply Current: 480mA
• Operating Supply Voltage (min): 3.14V
• Operating Supply Voltage (max): 3.47V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Word Size: 36b
• Lead Free Status / Rohs Status: Not Compliant

Document #: 38-05161 Rev. *B
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
ZZ Mode Electrical Characteristics
Truth Table
Notes:
10. CE = H means CE and CE
12. The device is not in Sleep Mode, i.e., the ZZ pin is LOW.
13. During Sleep Mode, the ZZ pin is HIGH and all the address pins and control pins are “Don’t Care.” The SNOOZE MODE can only be entered two cycles after
14. All inputs, except OE, ZZ, and MODE pins, must meet set-up time and hold time specification against the clock (CLK) LOW-to-HIGH transition edge.
15. OE may be tied to LOW for all the operation. This device automatically turns off the output driver during Write cycle.
16. Device outputs are ensured to be in High-Z during device power-up.
17. This device contains a two-bit burst counter. The address counter is incremented for all Continue Burst cycles. Address wraps to the initial address every fourth
18. Continue Burst cycles, whether Read or Write, use the same control signals. The type of cycle performed, Read or Write, depends upon the WEN control signal
19. Dummy Read and Abort Write cycles can be entered to set up subsequent Read or Write cycles or to increment the burst counter.
20. When an Ignore Clock Edge cycle enters, the output data (Q) will remain the same if the previous cycle is Read cycle or remain High-Z if the previous cycle is
11. BWa enables Write to byte “a” (DQa pins). BWb enables Write to byte “b” (DQb pins). BWc enables Write to byte “c” (DQc pins). BWd enables Write to byte “d”
I
t
t
Deselect Cycle
Continue Deselect/NOP
Read Cycle (Begin Burst)
Read Cycle (Continue Burst)
Dummy Read (Begin Burst)
Dummy Read (Continue Burst)
Write Cycle (Begin Burst)
Write Cycle (Continue Burst)
Abort Write (Begin Burst)
Abort Write (Continue Burst)
Ignore Clock Edge/NOP
6.
7.
8.
9.
DDZZ
ZZS
ZZREC
This assumes that CEN, CE, CE
All addresses, control and data-in are only required to meet set-up and hold time with respect to the rising edge of clock. Data out is valid after a clock-to-data
delay from the rising edge of clock.
DQc and DQd apply to 256K × 36 device only.
L means logic LOW. H means logic HIGH. X means Don’t Care. High-Z means High Impedance. BWx = L means [BWa*BWb*BWc*BWd] = LOW. BWx = H
means [BWa*BWb*BWc*BWd] = HIGH. BWc and BWd apply to 256K × 36 device only.
(DQd pins). DQc, DQd, BWc, and BWd apply to 256K × 36 device only.
the Write cycle, otherwise the Write cycle may not be completed.
burst cycle.
at the Begin Burst cycle. A Continue Deselect cycle can only be entered if a DESELECT cycle is executed first.
Write or DESELECT cycle.
Parameter
Operation
[9, 10, 11, 12, 13, 14, 15, 16, 17]
3
[18]
[20]
[19]
are LOW along with CE
[19]
[18, 19]
[18]
[18]
2
and CE
[18, 19]
Sleep mode standby current
Device operation to ZZ
ZZ recovery time
3
are all True.
Previous
Deselect
Cycle
Description
Read
Read
Write
Write
X
X
X
X
X
X
2
HIGH. CE = L means CE or CE
Address
External
External
External
External
Used
Next
Next
Next
Next
X
X
X
WEN ADV/LD
H
H
X
X
X
X
X
L
X
X
L
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CEs must remain inactive for the duration of
t
before going into the ZZ mode and before you want to come
back out of the ZZ mode.
ZZREC
3
are HIGH or CE
Test Conditions
ZZ > V
ZZ > V
after the ZZ input returns LOW. CEN needs to active
ZZ < 0.2V
H
H
H
H
H
H
L
L
L
L
L
DD
DD
CY7C1354A/GVT71256ZC36
CY7C1356A/GVT71512ZC18
– 0.2V
– 0.2V
2
CE
H
X
X
X
X
X
X
L
L
L
L
is LOW. CE = X means CE, CE
CEN
H
L
L
L
L
L
L
L
L
L
L
BWx
2t
Min.
X
X
X
X
X
X
H
H
X
L
L
CYC
OE
H
H
X
X
X
X
X
X
X
X
X
3
, and CE
2t
Max.
10
CYC
(2 cycles later)
Page 9 of 31
2
are Don’t Care.
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
DQ
Q
Q
D
D
–
Unit
mA
ns
ns