CY7C68013-128AC Cypress Semiconductor Corp, CY7C68013-128AC Datasheet - Page 23

• Manufacturer Part Number: CY7C68013-128AC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C68013-128AC

• Cpu Family: FX2LP
• Device Core: 8051
• Device Core Size: 8b
• Frequency (max): 48MHz
• Interface Type: I2C/USB
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Total Internal Ram Size: 8KB
• # I/os (max): 40
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Instruction Set Architecture: CISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 128
• Package Type: TQFP
• Lead Free Status / Rohs Status: Not Compliant

5.0
FX2 register bit definitions are described in the FX2 TRM in
greater detail.
Table 5-1. FX2 Register Summary
Document #: 38-08012 Rev. *F
Note:
E60A
E60B
E60C
E61A
E61B
E400 128 WAVEDATA
E480 384 reserved
E600
E601
E602
E603
E604
E605
E606
E607
E608
E609
E610
E611
E612
E613
E614
E615
E618
E619
E620
E621
E622
E623
E624
E625
E626
E627
E630
E630
E631
Hex Size Name
H.S.
H.S.
F.S.
6.
Read and writes to these register may require synchronization delay, see Technical Reference Manual for “Synchronization Delay.”
1
1
1
1
1
1
1
1
1
1
1
1
1
3
1
1
1
1
1
1
2
1
1
1
1
4
1
1
1
1
1
1
1
1
8
1
1
1
GPIF Waveform Memories
GENERAL CONFIGURATION
CPUCS
IFCONFIG
PINFLAGSAB
PINFLAGSCD
FIFORESET
BREAKPT
BPADDRH
BPADDRL
UART230
FIFOPINPOLAR
REVID
REVCTL
UDMA
GPIFHOLDTIME
reserved
ENDPOINT CONFIGURATION
EP1OUTCFG
EP1INCFG
EP2CFG
EP4CFG
EP6CFG
EP8CFG
reserved
EP2FIFOCFG
EP4FIFOCFG
EP6FIFOCFG
EP8FIFOCFG
reserved
EP2AUTOINLENH
[6]
EP2AUTOINLENL
[6]
EP4AUTOINLENH
[6]
EP4AUTOINLENL
[6]
EP6AUTOINLENH
[6]
EP6AUTOINLENL
[6]
EP8AUTOINLENH
[6]
EP8AUTOINLENL
[6]
reserved
EP2FIFOPFH
EP2FIFOPFH
EP2FIFOPFL
Register Summary
[6]
[6]
[6]
[6]
[6]
[6]
[6]
[6]
[6]
[6]
[6]
[6]
Description
GPIF Waveform Descriptor
0, 1, 2, 3 data
CPU Control & Status
Interface Configuration
(Ports, GPIF, slave FIFOs)
Slave FIFO FLAGA and
FLAGB Pin Configuration
Slave FIFO FLAGC and
FLAGD Pin Configuration
Restore FIFOS to default
state
Breakpoint Control
Breakpoint Address H
Breakpoint Address L
230 Kbaud internally
generated ref. clock
Slave FIFO Interface pins
polarity
Chip Revision
Chip Revision Control
MSTB Hold Time (for UDMA)
Endpoint 1-OUT Configura-
tion
Endpoint 1-IN Configuration
Endpoint 2 Configuration
Endpoint 4 Configuration
Endpoint 6 Configuration
Endpoint 8 Configuration
Endpoint 2 / slave FIFO con-
figuration
Endpoint 4 / slave FIFO con-
figuration
Endpoint 6 / slave FIFO con-
figuration
Endpoint 8 / slave FIFO con-
figuration
Endpoint 2 AUTOIN Packet
Length H
Endpoint 2 AUTOIN Packet
Length L
Endpoint 4 AUTOIN Packet
Length H
Endpoint 4 AUTOIN Packet
Length L
Endpoint 6 AUTOIN Packet
Length H
Endpoint 6 AUTOIN Packet
Length L
Endpoint 8 AUTOIN Packet
Length H
Endpoint 8 AUTOIN Packet
Length L
Endpoint 2 / slave FIFO Pro-
grammable Flag H
Endpoint 2 / slave FIFO Pro-
grammable Flag H
Endpoint 2 / slave FIFO Pro-
grammable Flag L
IFCLKSRC
FLAGB3
FLAGD3
NAKALL
DECIS
DECIS
VALID
VALID
VALID
VALID
VALID
VALID
PFC7
A15
PL7
PL7
PL7
PL7
D7
rv7
b7
A7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
3048MHZ
PKTSTAT
PKTSTAT
FLAGB2
FLAGD2
INFM1
INFM1
INFM1
INFM1
PFC6
A14
DIR
DIR
DIR
DIR
PL6
PL6
PL6
PL6
D6
rv6
b6
A6
0
0
0
0
0
0
0
0
0
0
0
0
0
PORTCSTB
OUT:PFC12
OUT:PFC12 OUT:PFC11 OUT:PFC10
IN:PKTS[2]
IFCLKOE
PKTEND
FLAGB1
FLAGD1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
OEP1
OEP1
OEP1
OEP1
PFC5
A13
PL5
PL5
PL5
PL5
D5
rv5
b5
A5
0
0
0
0
0
0
0
0
0
OUT:PFC11
IN:PKTS[1]
IFCLKPOL
AUTOOUT
AUTOOUT
AUTOOUT
AUTOOUT
CLKSPD1
FLAGB0
FLAGD0
TYPE0
TYPE0
TYPE0
TYPE0
TYPE0
TYPE0
SLOE
PFC4
A12
PL4
PL4
PL4
PL4
D4
A4
rv4
b4
0
0
0
0
0
0
0
0
0
OUT:PFC10
IN:PKTS[0]
CLKSPD0
FLAGA3
FLAGC3
AUTOIN
AUTOIN
AUTOIN
AUTOIN
ASYNC
BREAK
SLRD
PFC3
SIZE
SIZE
EP3
A11
PL3
PL3
PL3
PL3
D3
rv3
b3
A3
0
0
0
0
0
0
0
0
0
0
0
ZEROLENIN
ZEROLENIN
ZEROLENIN
ZEROLENIN
BPPULSE
GSTATE
FLAGA2
FLAGC2
CLKINV
SLWR
PFC2
PL10
PL10
EP2
A10
PL2
PL2
PL2
PL2
D2
rv2
b2
A2
0
0
0
0
0
0
0
0
0
0
0
0
0
HOLDTIME1 HOLDTIME0 00000000
230UART1
FLAGA1
FLAGC1
IFCFG1
dyn_out
CLKOE
BPEN
BUF1
BUF1
PFC9
PFC9
PFC1
EP1
PL9
PL1
PL9
PL1
PL9
PL1
PL9
PL1
rv1
b1
D1
A9
A1
EF
0
0
0
0
0
0
0
0
WORDWIDE 00000101 rbbbbbrb
WORDWIDE 00000101 rbbbbbrb
WORDWIDE 00000101 rbbbbbrb
WORDWIDE 00000101 rbbbbbrb
230UART0 00000000
IN:PKTS[2]
OUT:PFC8
8051RES
FLAGA0
FLAGC0
IFCFG0
enh_pkt
CY7C68013
BUF0
BUF0
PFC8
PFC0
EP0
PL8
PL0
PL8
PL0
PL8
PL0
PL8
PL0
rv0
D0
A8
A0
FF
b0
0
0
0
0
0
Page 23 of 48
Rev A, B -
Rev C, D -
00000010 rrbbbbbr
11000000
00000000
01000000
00000000 rrrrbbbr
00000000 rrbbbbbb
00000000
00000010
00000100
00000000
10100000 brbbrrrr
10100000 brbbrrrr
10100010 bbbbbrbb
10100000 bbbbrrrr
00000010 rrrrrbbb
00000000
00000010
00000000
00000010 rrrrrbbb
00000000
00000010
00000000
10001000 bbbbbrbb
10001000 bbbbbrbb
00000000
11100010 bbbbbrbb
11100000 bbbbrrrr
xxxxxxxx
xxxxxxxx
xxxxxxxx
xxxxxxxx
Default
Rev E -
Access
rrrrrrbb
rrrrrrbb
rrrrrrbb
rrrrrrbb
rrrrrrbb
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
W
R