CY7C68013-128AC Cypress Semiconductor Corp, CY7C68013-128AC Datasheet - Page 33

CY7C68013-128AC

Manufacturer Part Number
CY7C68013-128AC
Description
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CY7C68013-128AC

Cpu Family
FX2LP
Device Core
8051
Device Core Size
8b
Frequency (max)
48MHz
Interface Type
I2C/USB
Program Memory Type
ROMLess
Program Memory Size
Not Required
Total Internal Ram Size
8KB
# I/os (max)
40
Number Of Timers - General Purpose
3
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Instruction Set Architecture
CISC
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
128
Package Type
TQFP
Lead Free Status / Rohs Status
Not Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY7C68013-128AC
Manufacturer:
CY
Quantity:
1 000
Part Number:
CY7C68013-128AC
Manufacturer:
CYPRESS/赛普拉斯
Quantity:
20 000
9.5
Table 9-3. GPIF Synchronous Signals Parameters with Internally Sourced IFCLK
Table 9-4. GPIF Synchronous Signals Parameters with Externally Sourced IFCLK
Notes:
Document #: 38-08012 Rev. *F
13. Dashed lines denote signals with programmable polarity.
14. GPIF asynchronous RDY
15. IFCLK must not exceed 48 MHz.
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
IFCLK
SRY
RYH
SGD
DAH
SGA
XGD
XCTL
IFCLK
SRY
RYH
SGD
DAH
SGA
XGD
XCTL
Parameter
Parameter
GPIF Synchronous Signals
IFCLK Period
RDY
Clock to RDY
GPIF Data to Clock Set-up Time
GPIF Data Hold Time
Clock to GPIF Address Propagation Delay
Clock to GPIF Data Output Propagation Delay
Clock to CTL
IFCLK Period
RDY
Clock to RDY
GPIF Data to Clock Set-up Time
GPIF Data Hold Time
Clock to GPIF Address Propagation Delay
Clock to GPIF Data Output Propagation Delay
Clock to CTL
x
signals have a minimum set-up time of 50 ns when using internal 48-MHz IFCLK.
X
X
GPIFADR[8:0]
DATA(output)
to Clock Set-up Time
to Clock Set-up Time
DATA(input)
Figure 9-4. GPIF Synchronous Signals Timing Diagram
RDY
IFCLK
CTL
X
X
X
X
Output Propagation Delay
Output Propagation Delay
X
X
Description
Description
t
SRY
t
SGD
t
XCTL
N
t
XGD
t
valid
IFCLK
t
RYH
t
DAH
t
SGA
N+1
20.83
20.83
Min.
Min.
8.9
9.2
2.9
3.7
3.2
4.5
0
0
[14, 15]
[15]
[13]
Max.
Max.
10.7
11.5
200
7.5
6.7
11
15
CY7C68013
Page 33 of 48
Unit
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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