JS28F128P30T85 Micron Technology Inc, JS28F128P30T85 Datasheet - Page 5

• Manufacturer Part Number: JS28F128P30T85
• Manufacturer: Micron Technology Inc

Specifications of JS28F128P30T85

• Cell Type: NOR
• Density: 128Mb
• Access Time (max): 85/17ns
• Interface Type: Parallel/Serial
• Boot Type: Top
• Address Bus: 23b
• Operating Supply Voltage (typ): 1.8V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP
• Program/erase Volt (typ): 1.7 to 2/8.5 to 9.5V
• Sync/async: Async/Sync
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 1.7V
• Operating Supply Voltage (max): 2V
• Word Size: 16b
• Number Of Words: 8M
• Supply Current: 28mA
• Mounting: Surface Mount
• Pin Count: 56
• Lead Free Status / Rohs Status: Compliant

P30
1.0
1.1
1.2
August 2008
Order Number: 306666-12
Functional Description
Introduction
This document provides information about the Numonyx™ StrataFlash
Memory (P30) product and describes its features, operation, and specifications.
The Numonyx™ StrataFlash
of Numonyx™ StrataFlash
densities, the P30 device brings reliable, two-bit-per-cell storage technology to the
embedded flash market segment. Benefits include more density in less space, high-
speed interface, lowest cost-per-bit NOR device, and support for code and data
storage. Features include high-performance synchronous-burst read mode, fast
asynchronous access times, low power, flexible security options, and three industry
standard package choices. The P30 product family is manufactured using Intel
ETOX™ VIII process technology.
The P30 product family is also planned on the Intel
AC timing changes are noted in this datasheet, and should be taken into account for all
new designs.
Overview
This section provides an overview of the features and capabilities of the P30.
The P30 family provides density upgrades from 64-Mbit through 512-Mbit. This family
of devices provides high performance at low voltage on a 16-bit data bus. Individually
erasable memory blocks are sized for optimum code and data storage.
Upon initial power up or return from reset, the device defaults to asynchronous page-
mode read. Configuring the Read Configuration Register enables synchronous burst-
mode reads. In synchronous burst mode, output data is synchronized with a user-
supplied clock signal. A WAIT signal provides an easy CPU-to-flash memory
synchronization.
In addition to the enhanced architecture and interface, the device incorporates
technology that enables fast factory program and erase operations. Designed for low-
voltage systems, the
P30 supports read operations with V
V
fastest flash array programming performance with V
throughput. With V
power design. In addition to voltage flexibility, a dedicated VPP connection provides
complete data protection when V
A Command User Interface (CUI) is the interface between the system processor and all
internal operations of the device. An internal Write State Machine (WSM) automatically
executes the algorithms and timings necessary for block erase and program. A Status
Register indicates erase or program completion and any errors that may have occurred.
An industry-standard command sequence invokes program and erase automation. Each
erase operation erases one block. The Erase Suspend feature allows system software to
pause an erase cycle to read or program data in another block. Program Suspend
allows system software to pause programming to read other locations. Data is
programmed in word increments (16 bits).
PP
at 1.8 V or 9.0 V. Buffered Enhanced Factory Programming (BEFP) provides the
PP
at 1.8 V, VCC and VPP can be tied together for a simple, ultra low
®
®
memory devices. Offered in 64-Mbit up through 512-Mbit
Embedded Memory (P30) product is the latest generation
PP
≤ V
CC
at 1.8 V, and erase and program operations with
PPLK
.
*
PP
65nm process lithography. 65nm
at 9.0 V, which increases factory
®
Embedded
*
130 nm
Datasheet
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