LRS1331C Sharp Electronics, LRS1331C Datasheet - Page 11

• Manufacturer Part Number: LRS1331C
• Manufacturer: Sharp Electronics

Specifications of LRS1331C

• Lead Free Status / Rohs Status: Not Compliant

6. Status Register Definition
SR.2 = WORD WRITE SUSPEND STATUS (WWSS)
SR.7 = WRITE STATE MACHINE STATUS (WSMS)
SR.6 = BLOCK ERASE SUSPEND STATUS (BESS)
SR.5 = ERASE AND CLEAR BLOCK LOCK-BITS
SR.4 = WORD WRITE AND SET LOCK-BIT
SR.3 = F-V
SR.1 = DEVICE PROTECT STATUS (DPS)
SR.0 = RESERVED FOR FUTURE ENHANCEMENTS (R)
WSMS
1 = Ready
0 = Busy
1 = Block Erase Suspended
0 = Block Erase in Progress/Completed
1 = Error in Block Erase, Full Chip Erase or Clear Block
0 = Successful Block Erase, Full Chip Erase or Clear
1 = Error in Word Write or Set Block/Permanent
0 = Successful Word Write or Set Block/Permanent
1 = F-V
0 = F-V
1 = Word Write Suspended
0 = Word Write in Progress/Completed
1 = Block Lock-Bit, Permanent Lock-Bit and/or F-WP
0 = Unlocked
7
STATUS (ECBLBS)
Lock-Bits
Block Lock-Bits
STATUS (WWSLBS)
Lock-Bit
Lock-Bit
Lock Detected, Operation Abort
CCW
CCW
CCW
STATUS (VCCWS)
Low Detect, Operation Abort
OK
BESS
6
ECBLBS
5
WWSLBS
4
L R S 1 3 3 1 C
Notes:
Check SR.7 or F-RY/BY to determine Block Erase, Full Chip
Erase, Word Write or Lock-Bit configuration completion.
SR.6 - SR.1 are invalid while SR.7 = “0”.
If both SR.5 and SR.4 are “1”s after a Block Erase, Full Chip
Erase or Lock-Bit configuration attempt, an improper com-
mand sequence was entered.
SR.3 does not provide a continuous indication of F-V
level. The WSM (Write State Machine) interrogates and
indicates the F-V
Erase, Word Write, or Lock-Bit Configuration command
sequences. SR.3 is not guaranteed to reports accurate feedback
only when F-V
SR.1 does not provide a continuous indication of permanent
and block lock-bit and F-WP values. The WSM interrogates
the permanent lock-bit, block lock-bit and F-WP only after
Block Erase, Full Chip Erase, Word Write, or Lock-Bit Con-
figuration command sequences. It informs the system, depend-
ing on the attempted operation, if the block lock-bit is set,
permanent lock-bit is set and/or F-WP is V
block lock and permanent lock configuration codes after writ-
ing the Read Identifier Codes command indicates permanent
and block lock-bit status.
SR.0 is reserved for future use and should be masked out when
polling the status register.
VCCWS
3
CCW
CCW
WWSS
V
2
level only after Block Erase, Full Chip
CCWH
.
DPS
1
IL
. Reading the
R
0
Rev. 1.00
CCW
9