LRS1331C Sharp Electronics, LRS1331C Datasheet - Page 9

• Manufacturer Part Number: LRS1331C
• Manufacturer: Sharp Electronics

Specifications of LRS1331C

• Lead Free Status / Rohs Status: Not Compliant

5. Command Definitions for Flash Memory
5.1 Command Definitions
Notes:
1. Commands other than those shown above are reserved by SHARP for future device implementations and should not be used.
2. Bus operations are defined in 3. Truth Table.
3. XA = Any valid address within the device.
4. See Identifier Codes at next page.
5. See Write Protection Alternatives in section 5.3.
6. The clear block lock-bits operation simultaneously clears all block lock-bits.
7. If the permanent lock-bit is set, Set Block Lock-Bit and Clear Block Lock-Bits commands can not be done.
8. Once the permanent lock-bit is set, it cannot be cleared.
9. If the time between writing the Block Erase Resume command and writing the Block Erase Suspend command is shorter than
Read Array / Reset
Read Identifier Codes
Read Status Register
Clear Status Register
Block Erase
Full Chip Erase
Word Write
Block Erase and Word Write
Suspend
Block Erase and Word Write
Resume
Set Block Lock Bit
Clear Block Lock Bits
Set Permanent Lock Bit
IA = Identifier code address.
BA = Address within the block being erased, set block lock bit.
WA = Address of memory location to be written.
SRD = Data read from status register (See 6. Status Register Definition).
WD = Data to be written at location WA. Data is latched on the rising edge of F-WE or F-CE (whichever goes high first).
ID = Data read from identifier codes (See 5.2 Identifier Codes).
t
the operation.
ERES
and both commands are written repeatedly, a longer time is required than standard block erase until the completion of
Command
Bus Cycles
Required
1
2
1
2
2
2
1
1
2
2
2
2
(1)
Note
5,9
5,9
6,7
4
5
5
5
7
8
L R S 1 3 3 1 C
Oper
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
(2)
First Bus Cycle
Address
XA
XA
XA
XA
XA
XA
XA
XA
XA
XA
XA
XA
(3)
40H or
D0H
Data
FFH
B0H
90H
70H
50H
20H
30H
10H
60H
60H
60H
Oper
Write
Write
Write
Write
Write
Write
Read
Read
(2)
Second Bus Cycle
Address
WA
XA
BA
XA
BA
XA
XA
IA
(3)
Data
SRD
D0H
D0H
D0H
01H
F1H
WD
Rev. 1.00
ID
(3)
7