PCK2001DL NXP Semiconductors, PCK2001DL Datasheet - Page 8

• Manufacturer Part Number: PCK2001DL
• Manufacturer: NXP Semiconductors

Specifications of PCK2001DL

• Number Of Outputs: 18
• Operating Supply Voltage (max): 3.465V
• Operating Temp Range: 0C to 70C
• Propagation Delay Time: 5ns
• Operating Supply Voltage (min): 3.135V
• Mounting: Surface Mount
• Pin Count: 48
• Operating Supply Voltage (typ): 3.3V
• Package Type: SSOP
• Quiescent Current: 100uA
• Power Dissipation: 850mW
• Duty Cycle: 55%
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

Philips Semiconductors
I
I
Unbuffered SDRAM DIMM. All vendors are required to determine the legal issues associated with the manufacture of I
1. Address assignment: The clock driver in this specification uses the single, 7-bit address shown below. All devices can use the address if
2. Options: It is our understanding that metal mask options and other pinouts of this type of clock driver will be allowed to use the same
3. Slave/Receiver: The clock driver is assumed to require only slave/receiver functionality. Slave/transmitter functionality is optional.
4. Data Transfer Rate: 100 kbits/s (standard mode) is the base functionality required. Fast mode (400 kbits/s) functionality is optional.
5. Logic Levels: I
6. Data Byte Format: Byte format is 8 Bits as described in the following appendices.
7. Data Protocol: To simplify the clock I
NOTE: The acknowledgement bit is returned by the slave/receiver (the clock driver).
2002 Jun 03
2
2
C has been chosen as the serial bus interface to control the PCK2001. I
C CONSIDERATIONS
14.318–150 MHz I
only one master clock driver is used in a design. The address can be re-used for the CKBF device if no other conflicting I
used in the system.
The following address was confirmed by Philips on 09/04/96.
NOTE: The R/W# bit is used by the I
‘one’ indicates a request for data (READ) from the clock driver. Since the definition of the clock buffer only allows the controller to WRITE
data; the R/W# bit of the address will always be seen as ‘zero’. Optimal address decoding of this bit is left to the vendor.
address as the original CKBF device. I
option).
based on a 3.3 Volt supply.
The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been
transferred. Indexed bytes are not allowed. However, the SMBus controller has a more specific format than the generic I
The clock driver must meet this protocol which is more rigorous than previously stated I
of controller. The controller “writes” to the clock driver and if possible would “read” from the clock driver (the clock driver is a slave/receiver
only and is incapable of this transaction.)
“The block write begins with a slave address and a write condition. After the command code the host (controller) issues a byte count which
describes how many more bytes will follow in the message. If the host had 20 bytes to send, the first byte would be the number 20 (14h),
followed by the 20 bytes of data. The byte count may not be 0. A block write command is allowed to transfer a maximum of 32 data bytes.”
A6
1
A5
1
2
C logic levels are based on a percentage of V
A4
0
A3
1
1 bit
Ack
Start bit
2
1 bit
C 1:18 clock buffer
A2
0
2
Data Byte 1
2
C controller as a data direction bit. A ‘zero’ indicates a transmission (WRITE) to the clock device. A
2
C interface, the clock driver serial protocol was specified to use only block writes from the controller.
8 bits
C addresses are defined in terms of function (master clock driver) rather than form (pinout, and
A1
0
Slave Address
7 bits
A0
1
Ack
1
R/W
Data Byte 2
R/W#
0
1
8 bits
DD
Ack
1
for the controller and other devices on the bus. Assume all devices are
8
Command Code
2
Ack
C was chosen to support the JEDEC proposal JC-42.5 168 Pin
1
8 bits
...
Ack
Data Byte 2
1
8 bits
2
C protocol. Treat the description from the viewpoint
Byte Count = N
Ack
1
Stop
1
SW00279
2
C devices.
2
2
PCK2001
C protocol.
C clock driver is
Product data