PCK2001DL NXP Semiconductors, PCK2001DL Datasheet - Page 9

• Manufacturer Part Number: PCK2001DL
• Manufacturer: NXP Semiconductors

Specifications of PCK2001DL

• Number Of Outputs: 18
• Operating Supply Voltage (max): 3.465V
• Operating Temp Range: 0C to 70C
• Propagation Delay Time: 5ns
• Operating Supply Voltage (min): 3.135V
• Mounting: Surface Mount
• Pin Count: 48
• Operating Supply Voltage (typ): 3.3V
• Package Type: SSOP
• Quiescent Current: 100uA
• Power Dissipation: 850mW
• Duty Cycle: 55%
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

Philips Semiconductors
8. Clock stretching: The clock device must not hold/stretch the SCLOCK or SDATA lines low for more than 10 mS. Clock stretching is
9. General Call: It is assumed that the clock driver will not have to respond to the “general call.”
10. Electrical Characteristics: All electrical characteristics must meet the standard mode specifications found in section 15 of the I
a. Pull-Up Resistors: Any internal resistors pull-ups on the SDATA and SCLOCK inputs must be stated in the individual data sheet. The use of
b. Input Glitch Filters: Only fast mode I
11. PWR DWN#: If a clock driver is placed in PWR DWN# mode, the SDATA and SCLK inputs must be 3-Stated and the device must retain all
For specific I
2002 Jun 03
14.318–150 MHz I
Consider the command code and the byte count bytes required as the first two bytes of any transfer. The command code is software
programmable via the controller, but will be specified as 0000 0000 in the clock specification. The byte count byte is the number of
additional bytes required to transfer, not counting the command code and byte count bytes. Additionally, the byte count byte is required to
be a minimum of 1 byte and a maximum of 32 bytes to satisfy the above requirement.
For example:
A transfer is considered valid after the acknowledge bit corresponding to the byte count is read by the controller. The serial controller
interface can be simplified by discarding the information in both the command code and the byte count bytes and simply reading all the bytes
that are sent to the clock driver after being addressed by the controller. It is expected that the controller will not provide more bytes than the
clock driver can handle. A clock vendor may choose to discard any number of bytes that exceed the defined byte count.
discouraged and should only be used as a last resort. Stretching the clock/data lines for longer than this time puts the device in an
error/time-out mode and may not be supported in all platforms. It is assumed that all data transfers can be completed as specified without
the use of clock/data stretching.
specification.
internal pull-ups on these pins of below 100 k is discouraged. Assume that the board designer will use a single external pull-up resistor for
each line and that these values are in the 5 to 6 k range. Assume one I
one clock driver plus one/two more I
mode device and is not required to support this feature.
programming information. I
Byte count byte
MSB
0000
0000
0000
0000
0000
0000
0000
0000
0010
2
C information consult the Philips I
0000 Not allowed. Must have at least one byte.
0001 Data for functional and frequency select register (currently byte 0 in spec)
0010 Reads first two bytes of data. (byte 0 then byte 1)
0100 Reads first four bytes (byte 0, 1, 2, 3 in order)
0101 Reads first five bytes (byte 0, 1, 2, 3, 4 in order)
0000 Max byte count supported = 32
0011 Reads first three bytes (byte 0, 1, 2 in order)
0110 Reads first six bytes (byte 0, 1, 2, 3, 4, 5 in order)
0111 Reads first seven bytes (byte 0, 1, 2, 3, 4, 5, 6 in order)
LSB
DD
current due to the I
2
C 1:18 clock buffer
2
C devices on the platform for capacitive loading purposes.
2
C devices require input glitch filters to suppress bus noise. The clock driver is specified as a standard
2
C Peripherals Data Handbook IC12 (1997) .
2
C circuitry must be characterized and in the data sheet.
9
2
C device per DIMM (serial presence detect), one I
Notes:
PCK2001
2
C controller,
2
Product data
C