MB15F72ULPFT-G-BND Fujitsu Components, MB15F72ULPFT-G-BND Datasheet - Page 3

• Manufacturer Part Number: MB15F72ULPFT-G-BND
• Manufacturer: Fujitsu Components

Specifications of MB15F72ULPFT-G-BND

• Lead Free Status / Rohs Status: Not Compliant

■ PIN DESCRIPTION
TSSOP BCC
10
11
12
13
14
15
16
17
18
19
20
1
2
3
4
5
6
7
8
9
Pin no.
19
20
10
11
12
13
14
15
16
17
18
1
2
3
4
5
6
7
8
9
Pin name I/O
LD/fout
GND
OSC
GND
Xfin
Clock
GND
Xfin
V
PS
Data
V
D
Vp
PS
fin
Vp
D
fin
LE
CCRF
CCIF
ORF
OIF
RF
RF
IF
RF
IF
IF
RF
IF
RF
IN
IF
⎯ Ground for OSC input buffer and the shift register circuit.
⎯ Ground for the IF-PLL section.
⎯
⎯ Power supply voltage input pin for the IF-PLL charge pump.
⎯ Power supply voltage input pin for the RF-PLL charge pump.
⎯
⎯ Ground for the RF-PLL section
O Charge pump output pin for the IF-PLL section.
O
O Charge pump output pin for the RF-PLL section.
I
I
I
I
I
I
I
I
I
I
The programmable reference divider input. TCXO should be connected with an
AC coupling capacitor.
Prescaler input pin for the IF-PLL.
Connection to an external VCO should be via AC coupling.
Prescaler complimentary input pin for the IF-PLL section.
This pin should be grounded via a capacitor.
Power supply voltage input pin for the IF-PLL section (except for the charge
pump circuit) , the OSC input buffer and the shift register circuit.
Power saving mode control for the IF-PLL section. This pin must be set at “L”
when the power supply is started up. (Open is prohibited.)
PS
Lock detect signal output (LD) /phase comparator monitoring
output (fout) pins.The output signal is selected by LDS bit in the serial data.
LDS bit = “H” ; outputs fout signal / LDS bit = “L” ; outputs LD signal
Power saving mode control pin for the RF-PLL section. This pin must be set at
“L” when the power supply is started up. (Open is prohibited.)
PS
Power supply voltage input pin for the RF-PLL section (except for the charge
pump circuit)
Prescaler complimentary input pin for the RF-PLL section.
This pin should be grounded via a capacitor.
Prescaler input pin for the RF-PLL.
Connection to an external VCO should be via AC coupling.
Load enable signal input pin (with the schmitt trigger circuit)
When LE is set “H”, data in the shift register is transferred to the
corresponding latch according to the control bit in the serial data.
Serial data input pin (with the schmitt trigger circuit)
Data is transferred to the corresponding latch (IF-ref. counter, IF-prog. counter,
RF-ref. counter, RF-prog. counter) according to the control bit in
the serial data.
Clock input pin for the 23-bit shift register (with the schmitt trigger circuit)
One bit of data is shifted into the shift register on a rising edge of the clock.
IF
RF
= “H” ; Normal mode / PS
= “H” ; Normal mode / PS
IF
RF
= “L” ; Power saving mode
Descriptions
= “L” ; Power saving mode
MB15F72UL
3