MB15F72ULPFT-G-BND Fujitsu Components, MB15F72ULPFT-G-BND Datasheet - Page 8
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MB15F72ULPFT-G-BND
Manufacturer Part Number
MB15F72ULPFT-G-BND
Description
Manufacturer
Fujitsu Components
Datasheet
1.MB15F72ULPFT-G-BND.pdf
(28 pages)
Specifications of MB15F72ULPFT-G-BND
Lead Free Status / Rohs Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MB15F72ULPFT-G-BND-EFE1
Manufacturer:
Fujitsu
Quantity:
3 000
8
MB15F72UL
■ FUNCTIONAL DESCRIPTION
1. Pulse swallow function :
2. Serial Data Input
(1)
CN1
CN2
f
The serial data is entered using three pins, Data pin, Clock pin, and LE pin. Programmable dividers of IF/
RF-PLL sections, and programmable reference dividers of IF/RF-PLL sections are controlled individually.
The serial data of binary data is entered through Data pin.
On a rising edge of Clock, one bit of the serial data is transferred into the shift register. On a rising edge of load
enable signal, the data stored in the shift register is transferred to one of latches depending upon the control bit
data setting.
• Programmable Reference Counter
VCO
Shift Register Configuration
Note : Data input with MSB first.
f
P : Preset divide ratio of dual modulus prescaler (8 or 16 for IF-PLL, 64 or 128 for RF-PLL)
N : Preset divide ratio of binary 11-bit programmable counter (3 to 2,047)
A : Preset divide ratio of binary 7-bit swallow counter (0 ≤ A ≤ 127, A < N)
f
R : Preset divide ratio of binary 14-bit programmable reference counter (3 to 16,383)
CS
R1 to R14 : Divide ratio setting bits for the programmable reference counter (3 to 16,383)
T1, T2
CN1, CN2 : Control bit
X
CN1 CN2 T1 T2 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 CS
VCO
OSC
= [ (P × N) + A] × f
1
The programmable
: Output frequency of external voltage controlled oscillator (VCO)
: Reference oscillation frequency (OSC
reference counter
for the IF-PLL
2
(LSB)
3
: Charge pump current select bit
: LD/fout output setting bit.
: Dummy bits (Set “0” or “1”)
0
0
4
OSC
5
÷ R
6
The programmable
reference counter
7
for the RF-PLL
8
1
0
9 10 11 12 13 14
IN
Data Flow
input frequency)
counter and the swallow
counter for the IF-PLL
The programmable
15
0
1
16
17
18 19 20 21 22 23
counter and the swallow
counter for the RF-PLL
The programmable
(MSB)
X
1
1
X
X
X