GS8342T36AE-250 GSI TECHNOLOGY, GS8342T36AE-250 Datasheet - Page 7

• Manufacturer Part Number: GS8342T36AE-250
• Manufacturer: GSI TECHNOLOGY

Specifications of GS8342T36AE-250

• Density: 36Mb
• Access Time (max): 0.45ns
• Sync/async: Synchronous
• Architecture: DDR
• Clock Freq (max): 250MHz
• Operating Supply Voltage (typ): 1.8V
• Address Bus: 20b
• Package Type: FBGA
• Operating Temp Range: 0C to 70C
• Number Of Ports: 1
• Supply Current: 650mA
• Operating Supply Voltage (min): 1.7V
• Operating Supply Voltage (max): 1.9V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 165
• Word Size: 36b
• Number Of Words: 1M
• Lead Free Status / Rohs Status: Not Compliant

GS8342T08/09/18/36AE-333/300/250/200/167
Background
Common I/O SRAMs, from a system architecture point of view, are attractive in read dominated or block transfer applications.
Therefore, the SigmaCIO DDR-II SRAM interface and truth table are optimized for burst reads and writes. Common I/O SRAMs
are unpopular in applications where alternating reads and writes are needed because bus turnaround delays can cut high speed
Common I/O SRAM data bandwidth in half.
Burst Operations
Read and write operations are "burst" operations. In every case where a read or write command is accepted by the SRAM, it will
respond by issuing or accepting two beats of data, executing a data transfer on subsequent rising edges of K and K#, as illustrated
in the timing diagrams. It is not possible to stop a burst once it starts. Two beats of data are always transferred. This means that it is
possible to load new addresses every K clock cycle. Addresses can be loaded less often, if intervening deselect cycles are inserted.
Deselect Cycles
Chip Deselect commands are pipelined to the same degree as read commands. This means that if a deselect command is applied to
the SRAM on the next cycle after a read command captured by the SRAM, the device will complete the two beat read data transfer
and then execute the deselect command, returning the output drivers to high-Z. A high on the LD# pin prevents the RAM from
loading read or write command inputs and puts the RAM into deselect mode as soon as it completes all outstanding burst transfer
operations.
SigmaCIO DDR-II B2 SRAM Read Cycles
The SRAM executes pipelined reads. The status of the Address, LD# and R/W# pins are evaluated on the rising edge of K. The
read command (LD# low and R/W# high) is clocked into the SRAM by a rising edge of K. After the next rising edge of K, the
SRAM produces data out in response to the next rising edge of C# (or the next rising edge of K#, if C and C# are tied high). The
second beat of data is transferred on the next rising edge of C, for a total of two transfers per address load.
SigmaCIO DDR-II B2 SRAM Write Cycles
The status of the Address, LD# and R/W# pins are evaluated on the rising edge of K. The SRAM executes "late write" data
transfers. Data in is due at the device inputs on the rising edge of K following the rising edge of K clock used to clock in the write
command (LD# and R/W# low) and the write address. To complete the remaining beat of the burst of two write transfer, the SRAM
captures data in on the next rising edge of K#, for a total of two transfers per address load.
Rev: 1.05 12/2007
7/37
© 2006, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.