GS8342T36AE-250 GSI TECHNOLOGY, GS8342T36AE-250 Datasheet - Page 8

• Manufacturer Part Number: GS8342T36AE-250
• Manufacturer: GSI TECHNOLOGY

Specifications of GS8342T36AE-250

• Density: 36Mb
• Access Time (max): 0.45ns
• Sync/async: Synchronous
• Architecture: DDR
• Clock Freq (max): 250MHz
• Operating Supply Voltage (typ): 1.8V
• Address Bus: 20b
• Package Type: FBGA
• Operating Temp Range: 0C to 70C
• Number Of Ports: 1
• Supply Current: 650mA
• Operating Supply Voltage (min): 1.7V
• Operating Supply Voltage (max): 1.9V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 165
• Word Size: 36b
• Number Of Words: 1M
• Lead Free Status / Rohs Status: Not Compliant

Power-Up Sequence for SigmaQuad-II SRAMs
SigmaQuad-II SRAMs must be powered-up in a specific sequence in order to avoid undefined operations.
If the frequency is changed, DLL reset is required. After reset, a minimum of 1024 cycles is required for DLL lock.
Rev: 1.05 12/2007
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
V
V
V
V
V
DDQ
Doff
V
DDQ
Doff
REF
REF
DD
DD
K
K
K
K
Power-Up Sequence
DLL Constraints
Power UP Interval
Power UP Interval
1. Power-up and maintain Doff at low state.
2. After power is achieved and clocks (K, K, C, C) are stablized, change Doff to high.
3. An additional 1024 clock cycles are required to lock the DLL after it has been enabled.
Note:
The DLL may be reset by driving the Doff pin low or by stopping the K clocks for at least 30 ns. 1024 cycles of clean K clocks are always required to re-
lock the DLL after reset.
• The DLL synchronizes to either K or C clock. These clocks should have low phase jitter (t
• The DLL cannot operate at a frequency lower than that specified by the t
• If the incoming clock is not stablized when DLL is enabled, the DLL may lock on the wrong frequency and cause undefined errors or failures during
Note:
the initial stage.
1a.
1b. Apply V
1c.
Apply V
Apply V
DD
DDQ
REF
.
.
(may also be applied at the same time as V
Unstable Clocking Interval
Unstable Clocking Interval
Power-Up Sequence (Doff controlled)
Power-Up Sequence (Doff tied High)
8/37
DDQ
).
Stop Clock Interval
KHKH
30ns Min
GS8342T08/09/18/36AE-333/300/250/200/167
maximum specification for the desired operating clock frequency.
KCVar
DLL Locking Interval (1024 Cycles)
).
DLL Locking Interval (1024 Cycles)
© 2006, GSI Technology
Normal Operation
Normal Operation