AX500-2FG484 MICROSEMI, AX500-2FG484 Datasheet
AX500-2FG484
Specifications of AX500-2FG484
Available stocks
Related parts for AX500-2FG484
AX500-2FG484 Summary of contents
Page 1
... Unique In-System Diagnostic and Debug Capability with Actel Silicon Explorer II • Boundary-Scan Testing Compliant with IEEE Standard 1149.1 (JTAG) TM • FuseLock Secure Prevents Reverse Engineering and Design Theft AX125 AX250 AX500 125,000 250,000 500,000 82,000 154,000 286,000 672 1,408 2,688 ...
Page 2
... Fine Ball Grid Array (1.0mm pitch Chip Scale Package (0.8mm pitch Plastic Quad Flat Pack (0.5mm pitch Ceramic Quad Flat Pack (0.5mm pitch Ceramic Column Grid Array User I/Os (Including Clock Buffers) AX250 AX500 – – 115 115 115 115 – – ...
Page 3
... M = Military Packaging Data Refer to the following documents located on the Actel website for additional packaging information. Package Mechanical Drawings Package Thermal Characteristics and Weights Hermatic Package Mechanical Information Contact your local Actel representative for device availability. AX250 AX500 – – – – – ...
Page 4
Axcelerator Family FPGAs Table of Contents General Description Device Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 5
Table of Contents 1152-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 6
...
Page 7
General Description Axcelerator offers high performance at densities two million equivalent system gates. Based upon the Actel AX architecture, Axcelerator has several system- level features such as embedded SRAM (with complete FIFO control logic), PLLs, segmentable clocks, ...
Page 8
Axcelerator Family FPGAs Figure 1-2 • Axcelerator Family Interconnect Elements Logic Modules Actel's Axcelerator family provides two types of logic modules: the register cell (R-cell) and the combinatorial cell (C-cell). The can implement more than 4,000 combinatorial functions of up ...
Page 9
... DB CFN Figure 1-3 • AX C-Cell and R-Cell C C Figure 1-4 • AX SuperCluster Figure 1-5 • AX 2-bit Carry Logic Table 1-1 • Number of Core Tiles per Device Device AX125 AX250 AX500 AX1000 AX2000 FCI D E C-cell Y CLK (Positive Edge Triggered) FCO C-Cell ...
Page 10
Axcelerator Family FPGAs Chip Layout I/O Structure See Figure 7 Figure 1-6 • AX Device Architecture (AX1000 shown) Embedded Memory As mentioned earlier, each core tile has either three (in a smaller tile) or four (in the regular tile) embedded ...
Page 11
RAM/ FIFO RAM/ FIFO 4k RAM/ FIFO 4k RAM/ FIFO Figure 1-7 • I/O Cluster Arrangement Routing The AX hierarchical routing structure ties the logic modules, the embedded memory blocks, and the ...
Page 12
Axcelerator Family FPGAs Figure 1-8 • AX Routing Structures operating with input frequencies ranging from 14 MHz to 200 MHz and can generate output frequencies between 20 MHz and 1 GHz. The clock can be either divided or multiplied by ...
Page 13
With the Designer software, a user can lock the design pins before layout while minimally impacting the results of place-and-route. Additionally, Actel’s back-annotation flow is compatible with all the major simulators and the simulation results can be cross-probed with Silicon ...
Page 14
Axcelerator Family FPGAs Related Documents Application Notes Simultaneous Switching Noise and Signal Integrity http://www.actel.com/documents/SSN_AN.pdf Axcelerator Family PLL and Clock Management http://www.actel.com/documents/AX_PLL_AN.pdf Implementation of Security in Actel Antifuse FPGAs http://www.actel.com/documents/Antifuse_Security_AN.pdf User’s Guides and Manuals Antifuse Macro Library Guide http://www.actel.com/documents/libguide_UG.pdf SmartGen, FlashROM, ...