AX500-2FG484 MICROSEMI, AX500-2FG484 Datasheet - Page 8

• Manufacturer Part Number: AX500-2FG484
• Manufacturer: MICROSEMI

Specifications of AX500-2FG484

• Family Name: Axcelerator
• Number Of Usable Gates: 286000
• Number Of Logic Blocks/elements: 5376
• # Registers: 5376
• # I/os (max): 317
• Frequency (max): 870MHz
• Process Technology: 0.15um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 5376
• Ram Bits: 73728
• Device System Gates: 500000
• Propagation Delay Time: 0.74ns
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• Lead Free Status / Rohs Status: Not Compliant

Figure 1-2 • Axcelerator Family Interconnect Elements
Logic Modules
Actel's Axcelerator family provides two types of logic
modules: the register cell (R-cell) and the combinatorial
cell (C-cell). The
can implement more than 4,000 combinatorial functions
of up to five inputs
The R-cell contains a flip-flop featuring asynchronous
clear, asynchronous preset, and active-low enable control
signals
feature programmable clock polarity selectable on a
register-by-register
flexibility (e.g., easy mapping of dual-data-rate functions
into the FPGA) while conserving valuable clock resources.
The clock source for the R-cell can be chosen from the
hardwired clocks, routed clocks, or internal logic.
Two C-cells, a single R-cell, and two Transmit (TX) and two
Receive (RX) routing buffers form a Cluster, while two
Clusters comprise a SuperCluster
Each SuperCluster also contains an independent Buffer (B)
module, which supports buffer insertion on high-fanout
nets by the place-and-route tool, minimizing system
delays while improving logic utilization.
1 -2
Axcelerator Family FPGAs
(Figure 1-3 on page
(Figure 1-3 on page
basis.
This
1-3). The R-cell registers
(Figure 1-4 on page
provides
1-3).
additional
1-3).
v2.8
The logic modules within the SuperCluster are arranged
so that two combinatorial modules are side-by-side,
giving a C–C–R – C–C–R pattern to the SuperCluster. This
C–C–R
(minimum delay) of two-bit carry logic for improved
arithmetic performance
The AX architecture is fully fracturable, meaning that if
one or more of the logic modules in a SuperCluster are
used by a particular signal path, the other logic modules
are still available for use by other paths.
At the chip level, SuperClusters are organized into core
tiles, which are arrayed to build up the full chip. For
example, the AX1000 is composed of a 3x3 array of nine
core tiles. Surrounding the array of core tiles are blocks
of I/O Clusters and the I/O bank ring
page
SuperClusters and four SRAM blocks (176 SuperClusters
and three SRAM blocks for the AX250). The SRAM blocks
are arranged in a column on the west side of the tile
(Figure 1-6 on page
1-3). Each core tile consists of an array of 336
pattern
enables
1-4).
(Figure 1-5 on page
efficient
implementation
(Table 1-1 on
1-3).