AX500-2FG484 MICROSEMI, AX500-2FG484 Datasheet - Page 13

• Manufacturer Part Number: AX500-2FG484
• Manufacturer: MICROSEMI

Specifications of AX500-2FG484

• Family Name: Axcelerator
• Number Of Usable Gates: 286000
• Number Of Logic Blocks/elements: 5376
• # Registers: 5376
• # I/os (max): 317
• Frequency (max): 870MHz
• Process Technology: 0.15um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 5376
• Ram Bits: 73728
• Device System Gates: 500000
• Propagation Delay Time: 0.74ns
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• Lead Free Status / Rohs Status: Not Compliant

With the Designer software, a user can lock the design
pins before layout while minimally impacting the results
of place-and-route. Additionally, Actel’s back-annotation
flow is compatible with all the major simulators and the
simulation results can be cross-probed with Silicon
Explorer II, Actel’s integrated verification and logic
analysis tool. Another tool included in the Designer
software is the SmartGen core generator, which easily
creates popular and commonly used logic functions for
implementation into your schematic or HDL design.
Actel's Designer software is compatible with the most
popular FPGA design entry and verification tools from
EDA vendors, such as Mentor Graphics, Synplicity,
Synopsys, and Cadence Design Systems. The Designer
software is available for both the Windows and UNIX
operating systems.
Programming
Programming support is provided through Actel's Silicon
Sculptor II, a single-site programmer driven via a PC-
based GUI. In addition, BP Microsystems offers multi-site
programmers that provide qualified support for Actel
devices. Factory programming is available for high-
volume production needs.
Figure 1-9 • Probe Setup
Connection
Serial
Additional 14 Channels
Silicon Explorer II
(Logic Analyzer)
Connection
22 Pin
Connection
16 Pin
v2.8
In-System Diagnostic and Debug
Capabilities
The Axcelerator family of FPGAs includes internal probe
circuitry, allowing the designer to dynamically observe
and analyze any signal inside the FPGA without disturbing
normal device operation. Up to four individual signals can
be brought out to dedicated probe pins (PRA/B/C/D) on
the device. The probe circuitry is accessed and controlled
via Silicon Explorer II
verification and logic analysis tool that attaches to the
serial port of a PC and communicates with the FPGA via
the JTAG port (See
on page
Summary
Actel’s Axcelerator family of FPGAs extends the
successful SX-A architecture, adding embedded RAM/
FIFOs, PLLs, and high-speed I/Os. With the support of a
suite of robust software tools, design engineers can
incorporate high gate counts and fixed pins into an
Axcelerator design yet still achieve high performance
and efficient device utilization.
CH4/PRD
CH3/PRC
TMS
TDO
TCK
PRA
PRB
TDI
2-91).
Axcelerator FPGAs
"Silicon Explorer II Probe Interface"
(Figure
Axcelerator Family FPGAs
1-9), Actel's integrated
1-7