21554AA Intel, 21554AA Datasheet - Page 23

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21554AA

Manufacturer Part Number
21554AA
Description
Manufacturer
Intel
Datasheet

Specifications of 21554AA

Lead Free Status / Rohs Status
Supplier Unconfirmed
Signal and Default Information
A.1
21554 PCI-to-PCI Non-Transparent Bridge Evaluation Board User’s Guide
Test Pod Pin Outs
Test points are accessible through board mounted Header type connectors, which are referred to as
pods. The following tables give the schematic name of the signal that can be found at each pod pin.
All even numbered pod pins are grounded. All odd numbered pod pins connect to a unique signal
that is documented on the 21554 Bridge Reference Design Schematic.
Table A-1
lines. See
Table A-1. Secondary Bus Test Pods
Figure 1-1
associates the pod pin numbers to the secondary bus control signals and address and data
a.
Pod Pin
Pod Pin
Number
Number
All even numbered pod pins are wired to earth ground.
for the location of this connector.
11
13
15
11
13
15
1
3
5
7
9
1
3
5
7
9
a
a
S_AD<0:7>
S_DEVSEL
S_FRAME
S_TRDY
S_IRDY
S_STOP
S_PERR
S_SERR
S_PARR
S_AD7
S_AD6
S_AD4
S_AD3
S_AD2
S_AD1
S_AD0
S_A5
J10
J9
Secondary Address and Data Pods
Secondary Bus Control Signals
S_AD<8:15>
S_GNTC3
S_GNTC2
S_GNTC1
S_GNTC0
S_REQ3
S_REQ2
S_REQ1
S_REQ0
S_AD15
S_AD14
S_AD13
S_AD12
S_AD11
S_AD10
S_AD9
S_AD8
J17
J12
S_AD<16:23>
(no connection)
(no connection)
S_CBE3
S_CBE2
S_CBE1
S_CBE0
S_AD23
S_AD22
S_AD21
S_AD20
S_AD19
S_AD18
S_AD17
S_AD16
P_GNT
P_REQ
J13
J11
S_AD<24:31>
(no connection)
S_ACK64
S_REQ64
S_PAR64
S_CBE4
S_CBE5
S_CBE6
S_CBE7
S_AD31
S_AD30
S_AD29
S_AD28
S_AD27
S_AD26
S_AD25
S_AD24
J14
J8
A
A-3