ICS8430AY-61 IDT, Integrated Device Technology Inc, ICS8430AY-61 Datasheet - Page 14

• Manufacturer Part Number: ICS8430AY-61
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Frequency Synthesizerr

Specifications of ICS8430AY-61

• Number Of Elements: 1
• Supply Current: 155mA
• Pll Input Freq (min): 14MHz
• Pll Input Freq (max): 27MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Package Type: LQFP
• Output Frequency Range: 20.83 to 500MHz
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.465V
• Operating Temperature Classification: Commercial
• Pin Count: 32
• Lead Free Status / Rohs Status: Not Compliant

The following component footprints are used in this layout
example: All the resistors and capacitors are size 0603.
P
Place the decoupling capacitors C14 and C15 as close as pos-
sible to the power pins. If space allows, placing the decoupling
capacitor at the component side is preferred. This can reduce
unwanted inductance between the decoupling capacitor and the
power pin generated by the via.
Maximize the pad size of the power (ground) at the decoupling
capacitor. Maximize the number of vias between power (ground)
and the pads. This can reduce the inductance between the power
(ground) plane and the component power (ground) pins.
If V
filter R7, C11, and C16 in between. Place this RC filter as close
to the V
C
The component placements, locations and orientations should be
arranged to achieve the best clock signal quality. Poor clock signal
quality can degrade the system performance or cause system fail-
ure. In the synchronous high-speed digital system, the clock signal
is less tolerable to poor signal quality than other signals. Any ring-
ing on the rising or falling edge or excessive ring back can cause
system failure. The trace shape and the trace delay might be re-
stricted by the available space on the board and the component
location. While routing the traces, the clock signal traces should be
routed first and should be locked prior to routing other signal traces.
8430AY-61
OWER AND
LOCK
CCA
shares the same power supply with V
CCA
T
RACES AND
pin as possible.
G
ROUNDING
T
ERMINATION
PIN 1
U1
C14
C1
F
IGURE
C15
CC
7B. PCB B
, insert the RC
TL1, TL21N are 50 Ohm
traces and equal length
www.idt.com
500MH
OARD
C11
14
L
X1
AYOUT FOR
The matching termination resistors R1, R2, R3 and R4 should
be located as close to the receiver input pins as possible. Other
termination schemes can also be used but are not shown in
this example.
C
The crystal X1 should be located as close as possible to the
pins 24 (XTAL_OUT) and 25 (XTAL_IN). The trace length be-
tween the X1 and U1 should be kept to a minimum to avoid
unwanted parasitic inductance and capacitance. Other signal
traces should not be routed near the crystal traces.
R7
RYSTAL
• The traces with 50Ω transmission lines TL1 and TL2 at
• Keep the clock trace on the same layer. Whenever pos-
• To prevent cross talk, avoid routing other signal traces in
• Make sure no other signal trace is routed between the
TL1N
TL1
Z
FOUT and nFOUT should have equal delay and run ad-
jacent to each other. Avoid sharp angles on the clock trace.
Sharp angle turns cause the characteristic impedance to
change on the transmission lines.
sible, avoid any vias on the clock traces. Any via on the
trace can affect the trace characteristic impedance and
hence degrade signal quality.
parallel with the clock traces. If running parallel traces is
unavoidable, allow more space between the clock trace
and the other signal trace.
clock trace pair.
, C
C16
VCCA
ICS8430-61
RYSTAL
C2
LVPECL F
R1
R3
Close to the input
pins of the
receiver
-
TO
-3.3V, 2.5V D
R2
R4
REQUENCY
GND
VCC
VIA
ICS8430-61
S
IFFERENTIAL
YNTHESIZER
REV. D JULY 27, 2010