ICS8430AY-61 IDT, Integrated Device Technology Inc, ICS8430AY-61 Datasheet - Page 2

• Manufacturer Part Number: ICS8430AY-61
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Frequency Synthesizerr

Specifications of ICS8430AY-61

• Number Of Elements: 1
• Supply Current: 155mA
• Pll Input Freq (min): 14MHz
• Pll Input Freq (max): 27MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Package Type: LQFP
• Output Frequency Range: 20.83 to 500MHz
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.465V
• Operating Temperature Classification: Commercial
• Pin Count: 32
• Lead Free Status / Rohs Status: Not Compliant

F
NOTE: The functional description that follows describes op-
eration using a 16MHz crystal. Valid PLL loop divider values
for different crystal or input frequencies are defined in the In-
put Frequency Characteristics, Table 5, NOTE 1.
The ICS8430-61 features a fully integrated PLL and therefore
requires no external components for setting the loop band-
width. A parallel-resonant, fundamental crystal is used as the
input to the on-chip oscillator. The output of the oscillator is
divided by 16 prior to the phase detector. With a 16MHz crys-
tal, this provides a 1MHz reference frequency. The VCO of
the PLL operates over a range of 250MHz to 500MHz. The
output of the M divider is also applied to the phase detector.
The phase detector and the M divider force the VCO output
frequency to be M times the reference frequency by adjusting
the VCO control voltage. Note that for some values of M (ei-
ther too high or too low), the PLL will not achieve lock. The
output of the VCO is scaled by a divider prior to being sent to
each of the LVPECL output buffers. The divider provides a
50% output duty cycle.
The programmable features of the ICS8430-61 support two
input modes and to program the M divider and N output di-
vider. The two input operational modes are parallel and serial.
Figure 1 shows the timing diagram for each mode. In parallel
mode, the nP_LOAD input is initially LOW. The data on inputs
M0 through M8 and N0 through N2 is passed directly to the M
divider and N output divider. On the LOW-to-HIGH transition
of the nP_LOAD input, the data is latched and the M divider
remains loaded until the next LOW transition on nP_LOAD or
until a serial event occurs. As a result, the M and N bits can
be hard-wired to set the M divider and N output divider to a
8430AY-61
M0:M8, N0:N2
UNCTIONAL
S_CLOCK
nP_LOAD
nP_LOAD
S_LOAD
S_DATA
S_LOAD
D
ESCRIPTION
t
S
T1
F
t
H
IGURE
T0
1. P
N2
t
M, N
S
ARALLEL
N1
t
H
www.idt.com
Time
500MH
P
N0
S
ARALLEL
& S
ERIAL
2
M8
ERIAL
specific default state that will automatically occur during
power-up. The TEST output is LOW when operating in the
parallel input mode. The relationship between the VCO fre-
quency, the crystal frequency and the M divider is defined as
follows:
The M value and the required values of M0 through M8 are
shown in Table 3B, Programmable VCO Frequency Function
Table. Valid M values for which the PLL will achieve lock for a
16MHz reference are defined as 250 ≤ M ≤ 500. The frequency
out is defined as follows:
Serial operation occurs when nP_LOAD is HIGH and S_LOAD
is LOW. The shift register is loaded by sampling the S_DATA
bits with the rising edge of S_CLOCK. The contents of the
shift register are loaded into the M divider and N output di-
vider when S_LOAD transitions from LOW-to-HIGH. The M
divide and N output divide values are latched on the HIGH-to-
LOW transition of S_LOAD. If S_LOAD is held HIGH, data at
the S_DATA input is passed directly to the M divider and N
output divider on each rising edge of S_CLOCK. The serial
mode can be used to program the M and N bits and test bits
T1 and T0. The internal registers T0 and T1 determine the state
of the TEST output as follows:
L
OADING
Z
L
M7
L
, C
OADING
T1
0
0
1
1
OAD
M6
RYSTAL
fVCO =
LVPECL F
T0
O
0
1
0
1
PERATIONS
M5
fxtal x
16
-
TO
M4
-3.3V, 2.5V D
M
M3
fout = fVCO =
S_Data, Shift Register Input
REQUENCY
M2
Output of M divider
TEST Output
N
ICS8430-61
CMOS Fout
M1
LOW
fxtal x
16
S
M0
IFFERENTIAL
YNTHESIZER
t
REV. D JULY 27, 2010
S
M
N