DSP56301PW80B1 Freescale Semiconductor, DSP56301PW80B1 Datasheet - Page 60

• Manufacturer Part Number: DSP56301PW80B1
• Manufacturer: Freescale Semiconductor

Specifications of DSP56301PW80B1

• Device Core Size: 24b
• Format: Fixed Point
• Clock Freq (max): 80MHz
• Mips: 80
• Device Input Clock Speed: 80MHz
• Ram Size: 24KB
• Program Memory Size: Not RequiredKB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: TQFP
• Lead Free Status / Rohs Status: Not Compliant

Specifications
2-34
No.
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
Data Out Valid from Read Data Strobe Assertion
(No Wait States Inserted—HTA Asserted)
Data Out Valid Hold from Read Data Strobe Deassertion
Data Out High Impedance from Read Data Strobe Deassertion
Data In Valid Setup to Write Data Strobe Deassertion
Data In Valid Hold from Write Data Strobe Deassertion
HSAK Assertion from Data Strobe Assertion
HSAK Asserted Hold from Data Strobe Deassertion
HTA Active from Data Strobe Assertion
HTA Assertion from Data Strobe Assertion
(HBS Not Used—Tied to V
HTA Assertion from HBS Assertion
HTA Deasserted from Data Strobe Assertion
HTA Assertion to Data Strobe Deassertion
HTA High Impedance from Data Strobe Deassertion
HIRQ Asserted Pulse Width (HIRH = 0, HIRD = 1)
Data Strobe Deasserted Hold from HIRQ Deassertion
(HIRH = 0)
HIRQ Asserted Hold from Data Strobe Assertion (HIRH = 1)
HIRQ Deassertion from Data Strobe Assertion
(HIRH = 1, HIRD = 1)
HIRQ High Impedance from Data Strobe Assertion
(HIRH = 1, HIRD = 0)
HIRQ Active from Data Strobe Deassertion
(HIRH = 1, HIRD = 0)
HIRQ Deasserted Hold from Data Strobe Deassertion
HDRQ
HDRQ
HDRQ
HDAK Assertion to Data Strobe Assertion
HDAK Asserted Hold from Data Strobe Deassertion
HDBEN Deasserted Hold from Data Strobe Assertion
HDBEN Assertion from Data Strobe Assertion
HDBEN Asserted Hold from Data Strobe Deassertion
HDBEN Deassertion from Data Strobe Deassertion
HDBDR High Hold from Read Data Strobe Assertion
HDBDR Low from Read Data Strobe Assertion
HDBDR Low Hold from Read Data Strobe Deassertion
2
2
2
Asserted Hold from Data Strobe Assertion
Deassertion from Data Strobe Assertion
Deasserted Hold from Data Strobe Deassertion
1
Table 2-18.
1
1,6
1
Characteristic
CC
)
1,2,5
2,5
1,2,5
Universal Bus Mode Timing Parameters (Continued)
3
1
1,2
DSP56301 Technical Data, Rev. 10
1
1,2,5
1
3
1
1
1
1
1
1,2
3
4
1
1
1
4
3
1
3
1
3
100 MHz: 2.0 × T
100 MHz: 2.0 × T
100 MHz: 2.5 × T
100 MHz: 2.5 × T
100 MHz: 2.5 × T
80 MHz: 2.0 × T
80 MHz: 2.0 × T
80 MHz: 2.5 × T
80 MHz: 2.5 × T
80 MHz: 2.5 × T
100 MHz: 2.5 × T
80 MHz: 2.5 × T
(LT + 1) × T
Expression
1.5 × T
2.5 × T
2.5 × T
1.5 × T
C
C
C
C
C
− 6.0
C
C
C
C
C
C
C
C
C
C
C
C
+ 13.0
+ 13.0
+ 24.7
+ 24.7
+ 24.7
+ 12.2
+ 12.2
+ 21.5
+ 21.5
+ 21.5
+ 3.7
+ 3.0
7
38.0
38.0
19.0
18.8
31.3
31.3
18.8
35.0
Min
1.7
8.3
0.0
2.0
3.1
0.0
0.0
5.8
0.0
2.5
2.5
2.5
2.5
—
—
—
—
—
—
—
—
—
—
—
80 MHz
Max
18.9
12.0
30.0
17.1
15.3
55.9
55.9
55.9
22.2
22.2
22.2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Freescale Semiconductor
Min
32.2
32.2
14.0
15.0
25.0
25.0
15.0
28.0
1.3
6.6
0.0
2.0
2.5
0.0
0.0
4.6
0.0
2.0
2.0
2.0
2.0
—
—
—
—
—
—
—
—
—
—
—
100 MHz
Max
16.9
30.0
15.0
12.2
46.5
46.5
46.5
19.6
19.6
19.6
9.6
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns