DSP56301PW80B1 Freescale Semiconductor, DSP56301PW80B1 Datasheet - Page 8

• Manufacturer Part Number: DSP56301PW80B1
• Manufacturer: Freescale Semiconductor

Specifications of DSP56301PW80B1

• Device Core Size: 24b
• Format: Fixed Point
• Clock Freq (max): 80MHz
• Mips: 80
• Device Input Clock Speed: 80MHz
• Ram Size: 24KB
• Program Memory Size: Not RequiredKB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: TQFP
• Lead Free Status / Rohs Status: Not Compliant

Signals/Connections
1.1 Power
1.2 Ground
1-4
V
V
V
V
V
V
V
Note:
Ground Name
GND
GND
GND
GND
GND
Power Name
CCP
CCQ
CCA
CCD
CCN
CCH
CCS
P
P1
Q
A
D
These designations are package-dependent. Some packages connect all V
those packages, all power input except V
PLL Power
Isolated power for the Phase Lock Loop (PLL). The voltage should be well-regulated and the input should be provided
with an extremely low impedance path to the V
Quiet Power
Isolated power for the internal processing logic. This input must be tied externally to all other chip power inputs. The
user must provide adequate external decoupling capacitors.
Address Bus Power
Isolated power for sections of the address bus I/O drivers. This input must be tied externally to all other chip power
inputs. The user must provide adequate external decoupling capacitors.
Data Bus Power
Isolated power for sections of the data bus I/O drivers. This input must be tied externally to all other chip power inputs.
The user must provide adequate external decoupling capacitors.
Bus Control Power
Isolated power for the bus control I/O drivers. This input must be tied externally to all other chip power inputs. The user
must provide adequate external decoupling capacitors.
Host Power
Isolated power for the HI32 I/O drivers. This input must be tied externally to all other chip power inputs. The user must
provide adequate external decoupling capacitors.
ESSI, SCI, and Timer Power
Isolated power for the ESSI, SCI, and timer I/O drivers. This input must be tied externally to all other chip power inputs.
The user must provide adequate external decoupling capacitors.
PLL Ground
Ground dedicated for PLL use. The connection should be provided with an extremely low-impedance path to ground.
V
PLL Ground 1
Ground dedicated for PLL use. The connection should be provided with an extremely low-impedance path to ground.
Quiet Ground
Isolated ground for the internal processing logic. This connection must be tied externally to all other chip ground
connections. The user must provide adequate external decoupling capacitors.
Address Bus Ground
Isolated ground for sections of the address bus I/O drivers. This connection must be tied externally to all other chip
ground connections. The user must provide adequate external decoupling capacitors.
Data Bus Ground
Isolated ground for sections of the data bus I/O drivers. This connection must be tied externally to all other chip ground
connections. The user must provide adequate external decoupling capacitors.
CCP
should be bypassed to GND
DSP56301 Technical Data, Rev. 10
CCP
Table 1-2.
P
are labeled V
Table 1-3.
by a 0.47 μF capacitor located as close as possible to the chip package.
CC
CC
Power Inputs
power rail.
.
Grounds
Description
Description
CC
inputs except V
CCP
to each other internally. On
Freescale Semiconductor