TDA5252XT Infineon Technologies, TDA5252XT Datasheet
TDA5252XT
Specifications of TDA5252XT
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TDA5252XT Summary of contents
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Data Sheet, Version 1.1, 2007-02- ...
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... Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies failure of such components can reasonably be expected to cause the failure of that life-support device or system affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body support and/or maintain and sustain and/or protect human life ...
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heet, Versio n 1.1, 2 007-02- ...
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... Previous Version: 1 2006-12-12 Page Subjects (major changes since last revision) 72 indication of the ESD-integrity values For questions on technology, delivery and prices please contact the Infineon Technologies Offices in Germany or the Infineon Technologies Companies and Representatives worldwide: see our webpage at http://www.infineon.com ® ® ® ABM ...
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ASK/FSK 915MHz Wireless Transceiver TDA5252 G2 Product Info General Description The low power consumption single chip FSK/ASK Transceiver for half duplex low datarate communication in the 915MHz band. The IC offers a very high level of integration ...
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Table of Contents 1 Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents TX-Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Product Description 1.1 Overview The low power consumption single chip FSK/ASK Transceiver for the ISM frequency band 915MHz. The IC combines a very high level of integration and minimum external part count. The device contains a ...
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Application – Low Bitrate Communication Systems – Keyless Entry Systems – Remote Control Systems – Alarm Systems – Telemetry Systems – Electronic Metering – Home Automation Systems 1.4 Package Outlines Figure 1-1 PG-TSSOP-38 package outlines Data Sheet Product Description ...
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Functional Description 2.1 Pin Configuration VCC BUSMODE LF ____ ASKFSK __ RxTx LNI LNIx GND1 GNDPA PA VCC1 PDN PDP SLC VDD BUSDATA BUSCLK VSS XOUT Figure 2-1 Pin Configuration Data Sheet ...
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Pin Definitions and Functions Table 2-1 Pin Definition and Function Pin No. Symbol Equivalent I/O-Schematic 1 VCC 2 BUSMODE ASKFSK Data Sheet 350 2 200 350 4 11 TDA5252 G2 Version 1.1 ...
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RXTX 5 6 LNI 6 7 LNIX 8 GND1 8 9 GNDPA VCC1 Data Sheet 350 1.1V 7 180 180 PWDN PWDN see Pin see Pin 8 10 ...
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PDN 12 13 PDP 13 14 SLC 14 15 VDD 16 BUSDATA 16 17 BUSCLK 18 VSS Data Sheet 50k 50k PWDN 350 3k 50k 50k 350 3k PWDN 50k 50k 1.2uA 350 50k 50k 50k 50k 1.2uA see ...
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XOUT Vcc 20 XSWF 21 XIN 22 XSWA 23 XGND 24 EN Data Sheet 4k Vcc-860mV 150µA 125fF ..... 4pF 250fF ..... 8pF see Pin see Pin 22 350 24 14 TDA5252 G2 Version 1.1 ...
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RESET 25 26 CLKDIV 26 27 PWDDD 27 28 DATA 28 29 RSSI 29 Data Sheet Reset of the entire system (to default values), active low 110k 350 10p Clock output 350 Power Down input (active high), data detect ...
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GND 31 CQ2x 31 32 CQ2 33 CI2x 34 CI2 35 CQ1x 36 CQ1 37 CI1x 38 CI1 Data Sheet see Pin 8 Analog ground Pin for external Capacitor Q-channel, stage 2 Stage1:Vcc-630mV Stage2: Vcc-560mV II Q-channel, stage 2 ...
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Functional Block Diagram BUSMODE __ EN BUSCLK BUSDATA SLC 31 CQ2x 32 CQ2 33 CI2x 34 CI2 CQ1 CQ1 37 CI1x 38 CI1 (digital) (analog) (LNA/PA) Figure 2-2 Main Block Diagram Data Sheet Functional Description 17 ...
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Functional Block Description 2.4.1 Power Amplifier (PA) The power amplifier is operating in C-mode. It can be used in either high or low power mode. In high-power mode the transmit power is approximately +13dBm into 50 Ohm at 5V ...
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PLL Synthesizer The Phase Locked Loop synthesizer consists of two VCOs (i.e. transmit and receive VCO), a divider asynchronous divider chain with selectable overall division ratio, a phase detector with charge pump and a loop filter ...
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Receive Signal Strength Indicator (RSSI) generators are included in both limiters which produce DC voltages that are directly proportional to the input signal level in the respective channels. The resulting I- and Q-channel RSSI-signals are summed to the nominal RSSI ...
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ASK / FSK INTERNAL BUS Figure 2-5 Data Filter architecture 2.4.10 Data Slicer The data slicer is a fast comparator with a bandwidth of 100kHz. The self-adjusting threshold is generated by a RC-network (LPF use of one or ...
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Table 2-5 PwdDD Pin Operating States PwdDD VDD Ground/VSS 2.4.14 Timing and Data Control Unit The timing and data control unit contains a wake-up logic unit interface, a “data valid” detection unit and a set of configuration registers ...
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The DATA VALID DETECTOR contains a frequency window counter and an RSSI threshold comparator. The window counter uses the incoming data signal from the data slicer as the gating signal and the crystal oscillator frequency as the timebase to determine ...
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I C Bus Mode In this mode the BusMode pin (pin 2) = LOW and the EN pin (pin 24) = LOW. Data Transition: Data transition on the pin BusData can only occur when BusCLK is LOW. BusData transitions ...
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Bus Data Format Mode Table 2-7 Chip address Organization MSB Table 2 Bus Write Mode 8 Bit MSB CHIP ADDRESS LSB (WRITE) STA 1 1 ...
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Bus Data Format 3-wire Bus Mode Table 2-11 3-wire Bus Write Mode MSB SUB ADDRESS (WRITE) 00H...08H, 0DH, 0EH,0FH Table 2-12 3-wire Bus Read Mode MSB SUB ADDRESS (READ) 80H, 81H ...
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Subaddress Organization Table 2-13 Sub Addresses of Data Registers Write MSB ...
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Table 2-16 Sub Address 01H: FSK Bit Function Value Description D15 D14 D13 FSK+5 8pF D12 FSK+4 4pF D11 FSK+3 2pF shift: +FSK or D10 FSK+2 1pF D9 FSK+1 500fF D8 FSK+0 250fF FSK-5 4pF D4 FSK-4 ...
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Table 2-22 Sub Address 08H: RSSI_TH3 Bit Function Description D7 not used D6 SELECT 0= VCC, 1= RSSI D5 TH3_5 D4 TH3_4 D3 TH3_3 D2 TH3_2 D1 TH3_1 D0 TH3_0 Table 2-24 Bit Function ...
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Wakeup Logic SELF POLLING Figure 2-9 Wakeup Logic States Table 2-28 MODE settings: CONFIG register MODE_1 SLAVE MODE: The receive and transmit operation is fully controlled by an external control device via the respective RxTx, AskFsk, ...
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Note: The time delay between start of ON time and the 15µs LOW impulse is 2.6ms + 3 period of data rate. If ADC & Data Detect Logic are in continuous mode the 15µs LOW impulse is applied at PwdDD ...
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Figure 2-13 Data Valid Circuit D_OUT and RX_DATA_INV from the CONFIG register determine the output of data at Pin 28. RxTxint and TX_ON are internally generated signals and power down mode Data pin (Pin 28) is tied to ...
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With default settings the clock generating units are disabled during PD, therefore no clock is available at the clock output pin possible to offer a clock signal at the clock output pin every time (also during PD) if ...
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This means that the device needs t When activating TX it requires t For timing information refer to Table 4-3. For test purposes a TESTMODE is provided by the Sequencer as well. In this mode the BLOCK_PD register be set ...
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Table 2-29 CLK_DIV Output Selection Note: Data are valid 500 µs after the crystal oscillator is enabled (see Figure 2-15 and Figure 2- 16, t CLKSU ). Table 2-30 CLK_DIV ...
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To prevent wrong interpretation of the ADC information (read from Register 81H: ADC) you can use the ADC- Power Down feedback Bit (D7) and the SELECT feedback Bit (D6) which correspond to the actual measurement. Note: As shown in Section ...
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Application 3.1 LNA and PA Matching 3.1.1 RX/TX Switch SMA-connector Figure 3-1 RX/TX Switch The RX/TX-switch combines the PA-output and the LNA-input into a single 50 Ohm SMA- connector. Two pin-diodes are used as switching elements current ...
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RF I/O 50 Ohm SMA-connector grounded (with jumper or RX/TX-pin of IC) Figure 3-2 RX-Mode The RF-signal is able to run from the RF-input-SMA-connector to the LNA-input-pin LNI via C1, C2, C7, L3 and C9. R1 does not affect the ...
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Measured Magnitude of S11 of evalboard: Figure 3-3 S11 measured Above you can see the measured S11 of the evalboard. The –3dB-points are at 851MHz and 989MHz. So the 3dB-bandwidth is: = − 989 MHz U ...
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The noise figure of the LNA-input-matching network is equal to its losses. The input matching network is always a compromise of sensitivity and selectivity. The loaded Q should not get too high because of 2 reasons: more losses in the ...
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RF I/O 50 Ohm SMA-connector grounded (with jumper or RX/TX-pin of IC) Figure 3-4 TX_Mode R1 does not influence the matching because of its very high resistance. Due to the large capacitance of C1, C6 and C5 the circuit can ...
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Power-Amplifier The power amplifier operates in a high efficient class C mode. This mode is characterized by a pulsed operation of the power amplifier transistor at a current flow angle of θ<<π. A frequency selective network at the amplifier ...
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The diagram of Figure 3-7 has been measured directly at the PA-output at V the matching circuit of about 3dB will decrease the output power. As shown in the diagram, 250 Ohm ...
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As Figure 3-8 shows, detuning beyond the bandwidth of the matching circuit results in a significant increase of collector current of the power amplifier and in some loss of power. This diagram shows the data of the circuit of the ...
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The evalboard has been optimized for 3V. The load is about 250+j0 at 915MHz. A tuning-free realization requires a careful design of the components within the matching network. A simple linear CAE-tool will help to see the influence of tolerances ...
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Figure 3-10 Transmit Spectrum 300MHz 3.2 Crystal Oscillator The equivalent schematic of the crystal with its parameters specified by the crystal manufacturer can be taken from the subsequent figure. Here also the load capacitance of the crystal ...
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Therefore the Resonant Frequency the crystal is defined as π The Series Load Resonant Frequency f S ‘ of the crystal is defined as ...
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Table 3-1 Crystal and crystal oscilator dependency Independent variable C 1 > > frequency of quartz > L OSC > > The crystal oscillator in the TDA5252 is a NIC (negative impedance converter) oscillator type. The ...
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In case of small frequency deviations (up to +/- 1000 ppm), the desired load capacitances for FSK modulation are frequency depending and can be calculated with the formula below. + − ⋅ ---------- ⋅ ...
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To set the 3 different frequencies 3 different C capacitors can be combined to generate the necessary C Internal banks of switchable capacitors allow the finetuning of these frequencies. 3.2.2 Transmit/Receive ASK/FSK Frequency Assignment Depending on whether the device operates ...
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XOUT XIN XSWF 20 XSWA XGND 23 FSK LOW Figure 3-14 FSK modulation In receive mode the crystal oscillator frequency is set to yield a direct-to-zero conversion of ...
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tune1 ------------------------------------------------------------------------------------------------------- - The C-bank C can be varied over a range steps of 250fF for finetuning of the FSK tune2 receive frequency. In ...
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Table 3-2 Typical values of parasitic capacitances Name With the given parasitics the actual tune1 C = ------------------------------------------------------------------------------------------------------- ...
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-FSK: v1 tune1 +FSK: v2 tune2 FSK_RX tune2 To compensate frequency errors due to crystal and component tolerance C be varied. To enable this correction, half of the necessary capacitance ...
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Finetuning and FSK modulation relevant registers Case FSK-RX or ASK-TX (C tune2 ): Table 3-4 Sub Address 02H: XTAL_TUNING Bit Function D5 Nominal_Frequ_5 D4 Nominal_Frequ_4 D3 Nominal_Frequ_3 D2 Nominal_Frequ_2 D1 Nominal_Frequ_1 D0 Nominal_Frequ_0 Case FSK-TX or ASK-RX (C tune1 ...
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Chip and System Tolerances Quartz: fp=19.0625MHz; C1=8fF; C0=2.1pF; CL=20pF (typical values) Cv1=8.2pF, Cv2=6.8pF, Cv3=22pF Table 3-7 Internal Tuning Part Frequency set accuracy Temperature (-40...+85C) Supply Voltage(2.1...5.5V) Total Table 3-8 Default Setup (without internal tuning & without Pin21 usage) Part ...
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IQ bandwidth should be realized (see Section 3.3). 3.3 IQ-Filter The IQ-Filter should be set to values corresponding to the RF-bandwidth of the received RF signal via the bits ...
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Figure 3-18 IQ Filter and frequency characteristics of the receive system 3.4 Data Filter The Data-Filter should be set to values corresponding to the bandwidth of the transmitted Data signal via the bits of the LPF ...
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Limiter and RSSI The I/Q Limiters are DC coupled multistage amplifiers with offset-compensating feedback circuit and an overall gain of approximately 80dB each in the frequency range of 100Hz up to 350kHz. Receive Signal Strength Indicator (RSSI) generators are ...
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Figure 3-20 Limiter frequency characteristics 1300 1200 1100 1000 900 800 700 600 500 400 300 200 100 0 -120 Figure 3-21 Typ. RSSI Level (Eval Board) @3V Data Sheet f 3dB ...
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Data Slicer - Slicing Level The data slicer is an analog-to-digital converter necessary to generate a threshold value for the negative comparator input (data slicer). The TDA5255 offers an RC integrator and a peak detector which can ...
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Peak Detectors Table 3-13 Sub Address 00H: CONFIG Bit Function D15 SLICER The TDA5252 has two peak detectors built in, one for positive peaks in the data stream and the other for the negative ones. Necessary external components: Figure ...
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Signal Figure 3-24 Peak Detector timing Component calculation: (rule of thumb) ⋅ ≥ Ω 100k T – longest period of no signal change (LOW signal) L1 ⋅ ≥ Ω 100k ...
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Figure 3-25 Peak Detector as analog Buffer (v=1) 3.6.4 Peak Detector – Power Down Mode For a safe and fast threshold value generation the peak detector is turned on by the sequencer circuit (see Section 2.4.18) only after the entire ...
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Signal Vcc Neg. Peak Detector (pin12) Pos. Peak Detector (pin13) 0 Power ON Figure 3-27 Power down mode 3.7 Data Valid Detection In order to detect valid data two criteria must be fulfilled. One criteria is the data rate, which ...
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Note 1: Chip internal signal „Sequencer enables data detection“ has a LOW to HIGH transition about 2.6ms after RX is activated (see Figure 2-15). Note 2: The positive edge of the „Window Count Complete“ signal latches the result of comparison ...
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Figure 3-30 Window Counter timing Example to calculate the thresholds for a given data rate: - Data signal manchester coded - Data Rate: 2kbit// 19.0625 MHz clk Then the period equals to respectively the high time is ...
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TH3 As an example a desired RSSI threshold voltage of 500mV results in TH3~26=011010 b , which has to be written into the RSSI_TH3 register (sub address 08H). Default value (RSSI detection inactive): TH3=111111 ...
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Frames Frame- details Sync Figure 3-31 Example for transmitted Data-structure According to existing synchronization techniques there are some synchronization bursts in front of the data added (code violation!). A minimum of 4 Frames is transmitted. Data are preferably Manchester ...
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Case A: Case B: Case C: Figure 3-32 3 possible timings Description: Assumption: the ON time comes right after the first frame (Case A). If OFF time is 135ms the receiver turns on during Sync-pulses and the PwdDD- pulse wakes ...
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Default Setup Default setup is hard wired on chip and effective after a reset or return of power supply. Table 3-14 Default Setup Parameter IQ-Filter Bandwidth Data Filter Bandwidth Limiter lower fg Slicing Level Generation Nom. Frequency Capacity intern ...
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Reference 4.1 Electrical Data 4.1.1 Absolute Maximum Ratings WARNING The maximum ratings may not be exceeded under any circumstances, not even momentarily and individually, as permanent damage to the IC may result. The AC/DC characteristic limits are not guaranteed. ...
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AC/DC Characteristics AC/DC characteristics involve the spread of values guaranteed within the specified voltage and ambient temperature range. Typical characteristics are the median of the production. The device performance paramter marked with x are not part of the production ...
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Table 4-3 AC/DC Characteristics with T # Parameter TRANSMITTER Characteristics 1 Supply current TX, FSK 2 Supply current TX, FSK 3 Supply current TX, FSK 4 Output power 5 Output power 6 Output power 7 Supply current TX, FSK 8 ...
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Table 4-4 AC/DC Characteristics with T # Parameter GENERAL Characteristics 1 Power down current timer mode (standby) 2 Power down current timer mode (standby) 3 Power down current with XTAL ON 4 Power down current with XTAL ON 5 32kHz ...
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Digital Characteristics Bus Timing BusMode = LOW t BUF BusData BusCLK H D. HIG H EN pulsed or t mandatory low SU. ENAS DA t SU. ENAS DA ...
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Table 4-5 Digital Characteristics with T # Parameter 1 Data rate TX ASK 2 Data rate TX ASK 3 Data rate TX FSK 4 Data rate RX ASK 5 Data rate RX FSK 6 Digital Inputs High-level Input Voltage Low-level ...
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Table 4-5 Digital Characteristics with T # Parameter 14 LOW period of BusCLK clock 15 HIGH period of BusCLK clock 16 Setup time for a repeated START condition 17 Data hold time 18 Data setup time 19 Rise, fall time ...
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Test Circuit The device performance parameters marked with or measured on an Infineon evaluation board (IFX board). Figure 4-3 Schematic of the Evaluation Board Data Sheet X in Section 4.1.3 were either verified by design 79 TDA5252 G2 Version ...
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Test Board Layout Gerberfiles for this Testboard are available on request. Figure 4-4 Layout of the Evaluation Board Note 1: The LNA and PA matching network was designed for minimum required space and maximum performance and thus via holes ...
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Bill of Materials Table 4-6 Bill of Materials Reference R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 ...
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Table 4-6 Bill of Materials Reference C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 IC1 IC2 IC3 D1 Data Sheet Value ...
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List of Tables Table 2-1 Pin Definition and Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Tables Table 3-13 Sub Address 00H: CONFIG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Figures Figure 1-1 PG-TSSOP-38 package outlines page Figure 2-1 Pin Configuration. ...
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List of Figures Figure 3-25 Peak Detector as analog Buffer (v= page Figure 3-26 Peak detector ...