T5743N-TGQ Atmel, T5743N-TGQ Datasheet - Page 16

• Manufacturer Part Number: T5743N-TGQ
• Manufacturer: Atmel

Specifications of T5743N-TGQ

• Operating Frequency (max): 450000kHz
• Operating Temperature (min): -40C
• Operating Temperature (max): 105C
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Lead Free Status / Rohs Status: Not Compliant

The delay of the data clock is calculated as follows:
t
t
and Data_In. For the rising edge, t
capacitive load C
resistor R
tionally on the external voltage V
T5743N
Delay
Delay1
16 (34)
Dem_out
Data_out (DATA)
DATA_CLK
= t
is the delay between the internal signals Data_Out
Delay1
pup
. For the falling edge, t
+ t
L
Delay2
at Pin DATA and the external pull–up
Figure 27. Timing characteristic of the data clock (falling edge of the Pin DATA)
Serial bi–directional
data line
Data_In
DATA_CLK
Data_Out
Data_Out
Serial bi–directional
data line
Data_In
DATA_CLK
Figure 26. Timing characteristic of the data clock (rising edge on Pin DATA)
’1’
Figure 25. Output of the data clock after a successful bit check
Receiving mode,
bit check active
Bit check ok
X
(see figures 26, 27 and
Delay1
Delay1
’1’
V
V
Il
Ih
= 0,65 * V S
= 0,35 * V S
depends on the
depends addi-
’1’
V
X
’1’
t
Delay1
t
Delay
t
Delay1
t
Delay
’1’
t
Delay2
34). When the level of Data_In is equal to the level of
Data_Out, the data clock is issued after an additional
delay t
Note that the capacitive load at Pin DATA is limited. If the
maximum tolerated capacitive load at Pin DATA is ex-
ceeded, the data clock disappears (see chapter ’Data
Interface’).
t
P_Data_Clk
t
Delay2
t
P_Data_Clk
Data
Start bit
’0’
Delay2
V
V
V
X
Ih
Il
= 0,35 * VS
= 0,65 * VS
Receiving mode,
data clock control
logic active
’1’
.
’1’
’0’
’1’
Rev. A3, 17-Dec-01
’0’