TDA18271HD/C2.557 NXP Semiconductors, TDA18271HD/C2.557 Datasheet - Page 13

• Manufacturer Part Number: TDA18271HD/C2.557
• Manufacturer: NXP Semiconductors

Specifications of TDA18271HD/C2.557

• Lead Free Status / Rohs Status: Compliant

NXP Semiconductors
Table 7.
TDA18271HD_4
Product data sheet
Address Byte
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
Extended bytes
10h
13h
16h
17h
19h
1Bh
1Ch
1Dh
21h
23h
24h
25h
26h
CPD
CD1
CD2
CD3
MPD IF_NOTCH
MD1
MD2
MD3
EB1
EB4
EB7
EB8
EB10 CID_GAIN[5:0]
EB12 PD_AGC1_DET
EB13 RFC_K[2:0]
EB14 RFC_CPROG[7:0]
EB18 AGC1_LOOP_OFF
EB20 FORCE_LOCK
EB21 AGC2_LOOP_OFF
EB22 RF_TOP[2:0]
EB23 FORCELP_FC2_EN
I
2
C-bus register bits explanation
9.3.1 I
Symbol
CAL_POST_DIV[7:0]
CAL_DIV[22:16]
CAL_DIV[15:8]
CAL_DIV[7:0]
MAIN_POST_DIV[6:0] LO synthesizer post-divider bits
MAIN_DIV[22:16]
MAIN_DIV[15:8]
MAIN_DIV[7:0]
CALVCO_FORLON
AGC1_ALWAYS_
MASTERN
AGC1_FIRSTN
LO_FORCESRCE
CAL_FORCESRCE
CID_ALARM
PD_AGC2_DET
RFC_M[1:0]
AGC1_GAIN[1:0]
AGC2_GAIN[1:0]
IF_TOP[3:0]
LP_FC
The programmable module address bits MA[1:0] allow up to four tuners to be addressed
in one system. Bits MA1 and MA0 are programmed by a specific voltage (V
pin AS. The relationship between the status of bits MA[1:0] and the voltage applied to pin
AS is shown in
2
C-bus address selection
Table
Description
calibration synthesizer post-divider
calibration synthesizer main divider bits
adds a DC notch in IF for a better adjacent channels rejection;
depends on standards
LO synthesizer main divider bits
determines which VCO is used during Normal mode operations
enables AGC1 normal operation whatever the tuner type (master or
slave)
determines which AGC (1 or 2) will be detected when detectors 1
and 2 are up
forces the main PLL charge pump to source current to the main PLL
loop filter
forces the calibration PLL charge pump to source current to the
calibration PLL loop filter
indicates that signal sensed by the power detector used during
calibrations is out of range
calibration power detector output
power-down of AGC1 detector
power-down of AGC2 detector
parameter used during the RF tracking filter calibration
parameter used during the RF tracking filter calibration
tuning word of the RF tracking filters
turns off the AGC1 loop
AGC1 gain
forces the internal PLLs lock indicator to logic 1
turns off the AGC2 loop
AGC2 gain
Take-Over Point (TOP) of the RF AGC, detection in RF
TOP of the RF AGC, detection in IF
FM filter selection
…continued
8.
Rev. 04 — 19 May 2009
TDA18271HD
© NXP B.V. 2009. All rights reserved.
Silicon Tuner IC
AS
) applied to
Reference
Table 20
Table 21
Table 22
Table 23
Table 24
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