SST39SF512-70-4C-NH Microchip Technology, SST39SF512-70-4C-NH Datasheet - Page 3

• Manufacturer Part Number: SST39SF512-70-4C-NH
• Description: Flash 64K X 8 70ns
• Manufacturer: Microchip Technology

Specifications of SST39SF512-70-4C-NH

• Data Bus Width: 8 bit
• Memory Type: NAND
• Memory Size: 512 Kbit
• Architecture: Sectored
• Interface Type: Parallel
• Access Time: 70 ns
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Maximum Operating Current: 50 mA
• Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: PLCC-32
• Organization: 64 KB x 8
• Lead Free Status / Rohs Status: No

512 Kbit Multi-Purpose Flash
SST39SF512
Data# Polling (DQ
When the SST39SF512 are in the internal Program opera-
tion, any attempt to read DQ
of the true data. Once the Program operation is completed,
DQ
may have valid data immediately following the completion
of an internal Write operation, the remaining data outputs
may still be invalid: valid data on the entire data bus will
appear in subsequent successive Read cycles after an
interval of 1 µs. During internal Erase operation, any
attempt to read DQ
Erase operation is completed, DQ
Data# Polling is valid after the rising edge of fourth WE# (or
CE#) pulse for Program Operation. For sector or Chip-
Erase, the Data# Polling is valid after the rising edge of
sixth WE# (or CE#) pulse. See Figure 7 for Data# Polling
timing diagram and Figure 16 for a flowchart.
Toggle Bit (DQ
During the internal Program or Erase operation, any con-
secutive attempts to read DQ
and 1s, i.e., toggling between 0 and 1. The Toggle Bit will
begin with “1”. When the internal Program or Erase opera-
tion is completed, the toggling will stop. The device is then
ready for the next operation. The Toggle Bit is valid after the
rising edge of fourth WE# (or CE#) pulse for Program oper-
ation. For Sector or Chip-Erase, the Toggle Bit is valid after
the rising edge of sixth WE# (or CE#) pulse. See Figure 8
for Toggle Bit timing diagram and Figure 16 for a flowchart.
Data Protection
The SST39SF512 provide both hardware and software fea-
tures to protect nonvolatile data from inadvertent writes.
Hardware Data Protection
Noise/Glitch Protection: A WE# or CE# pulse of less than 5
ns will not initiate a Write cycle.
V
inhibited when V
Write Inhibit Mode: Forcing OE# low, CE# high, or WE#
high will inhibit the Write operation. This prevents inadvert-
ent writes during power-up or power-down.
©2003 Silicon Storage Technology, Inc.
DD
7
Power Up/Down Detection: The Write operation is
will produce true data. Note that even thought DQ
DD
is less than 2.5V.
7
6
)
will produce a ‘0’. Once the internal
7
)
7
will produce the complement
6
will produce alternating 0s
7
will produce a ‘1’. The
7
3
Software Data Protection (SDP)
The SST39SF512 provide the JEDEC approved Software
Data Protection scheme for all data alteration operations,
i.e., Program and Erase. Any Program operation requires
the inclusion of a series of three byte sequence. The three-
byte load sequence is used to initiate the Program opera-
tion, providing optimal protection from inadvertent Write
operations, e.g., during the system power-up or power-
down. Any Erase operation requires the inclusion of six-
byte load sequence. The SST39SF512 device is shipped
with the Software Data Protection permanently enabled.
See Table 4 for the specific software command codes. Dur-
ing SDP command sequence, invalid commands will abort
the device to read mode, within T
Product Identification
The Product Identification mode identifies the device as the
SST39SF512 and SST39SF010 and manufacturer as
SST. This mode may be accessed by software operations.
Users may use the software Product Identification opera-
tion to identify the part (i.e., using the device ID) when using
multiple manufacturers in the same socket. For details,
Table 4 for software operation, Figure 11 for the software ID
entry and read timing diagram and Figure 17 for the ID
entry command sequence flowchart.
TABLE 1: P
Product Identification Mode Exit/Reset
In order to return to the standard Read mode, the Software
Product Identification mode must be exited. Exit is accom-
plished by issuing the Software ID Exit command
sequence, which returns the device to the Read operation.
Please note that the software reset command is ignored
during an internal Program or Erase operation. See Table 4
for software command codes, Figure 12 for timing wave-
form and Figure 17 for a flowchart.
Manufacturer’s ID
Device ID
SST39SF512
RODUCT
I
DENTIFICATION
RC.
Address
0000H
0001H
S71149-05-000
Data Sheet
Data
BFH
B4H
T1.3 1149
11/03