ispLSI2032-80LJ Lattice, ispLSI2032-80LJ Datasheet - Page 8
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ispLSI2032-80LJ
Manufacturer Part Number
ispLSI2032-80LJ
Description
CPLD - Complex Programmable Logic Devices USE ispMACH 4000V
Manufacturer
Lattice
Datasheet
1.ISPLSI_2032A-80LJ44.pdf
(16 pages)
Specifications of ispLSI2032-80LJ
Number Of Macrocells
32
Maximum Operating Frequency
84 MHz
Delay Time
18.5 ns
Number Of Programmable I/os
32
Operating Supply Voltage
4.75 V to 5.25 V
Supply Current
40 mA
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Package / Case
PLCC-48
Mounting Style
SMD/SMT
Supply Voltage (max)
5.25 V
Supply Voltage (min)
4.75 V
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ISPLSI2032-80LJ
Manufacturer:
LATTICE
Quantity:
5 510
Company:
Part Number:
ISPLSI2032-80LJ
Manufacturer:
ROCKWELL
Quantity:
5 510
Part Number:
ISPLSI2032-80LJ
Manufacturer:
ISPLSI
Quantity:
20 000
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR adjacent path can only be used by hard macros.
PARAMETER
Internal Timing Parameters
Inputs
t
t
GRP
t
GLB
t
t
t
t
t
t
t
t
t
t
t
t
t
ORP
t
t
Outputs
t
t
t
t
t
Clocks
t
t
Global Reset
t
io
din
grp
4ptbpc
4ptbpr
1ptxor
20ptxor
xoradj
gbp
gsu
gh
gco
gro
ptre
ptoe
ptck
orp
orpbp
ob
sl
oen
odis
goe
gy0
gy1/2
gr
20 Input Buffer Delay
21 Dedicated Input Delay
22 GRP Delay
23 4 Product Term Bypass Path Delay (Combinatorial)
24 4 Product Term Bypass Path Delay (Registered)
25 1 Product Term/XOR Path Delay
26 20 Product Term/XOR Path Delay
27 XOR Adjacent Path Delay
28 GLB Register Bypass Delay
29 GLB Register Setup Time befor Clock
30 GLB Register Hold Time after Clock
31 GLB Register Clock to Output Delay
32 GLB Register Reset to Output Delay
33 GLB Product Term Reset to Register Delay
34 GLB Product Term Output Enable to I/O Cell Delay
35 GLB Product Term Clock Delay
36 ORP Delay
37 ORP Bypass Delay
38 Output Buffer Delay
39 Output Slew Limited Delay Adder
40 I/O Cell OE to Output Enabled
41 I/O Cell OE to Output Disabled
42 Global Output Enable
43 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock)
44 Clock Delay, Y1 or Y2 to Global GLB Clock Line
45 Global Reset to GLB
#
2
Over Recommended Operating Conditions
1
DESCRIPTION
3
8
Specifications ispLSI 2032/A
MIN.
0.5
4.0
4.0
3.2
3.2
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
-110
MAX.
10.0
1.5
0.5
1.2
4.0
4.0
3.0
3.2
3.2
9.0
1.7
3.4
4.9
4.8
6.2
6.8
7.5
0.1
0.6
1.8
5.9
7.1
1.7
7.0
–
–
MIN.
0.1
6.0
5.5
4.6
4.6
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
-80
Table 2-0036C-110/2032
MAX.
10.2
12.8
10.0
12.8
2.2
4.8
2.6
7.2
7.2
8.8
9.2
0.0
0.4
2.2
8.8
9.5
2.1
0.6
2.4
6.4
6.4
5.6
4.6
4.6
–
–
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns