A43L3616AV-7F AMIC, A43L3616AV-7F Datasheet - Page 21

• Manufacturer Part Number: A43L3616AV-7F
• Description: 58T1326
• Manufacturer: AMIC

Specifications of A43L3616AV-7F

• Memory Type: SDRAM
• Memory Configuration: 8M X 16
• Access Time: 5.4ns
• Interface Type: LVTTL
• Memory Case Style: TSOPII
• No. Of Pins: 54
• Operating Temperature Range: 0°C To +70°C
• Frequency: 143MHz
• Rohs Compliant: Yes

11. About Burst Type Control
12. About Burst Length Control
PRELIMINARY (January, 2009, Version 0.6)
Random
Interrupt
Special
MODE
MODE
MODE
MODE
MODE
* Note : 1. Active power down : one or more bank active state.
Basic
Basic
2. Precharge power down : both bank precharge state.
3. The auto refresh is the same as CBR refresh of conventional DRAM.
4. Before executing auto/self refresh command, both banks must be idle state.
5. MRS, Bank Active, Auto/Self Refresh, Power Down Mode Entry.
6. During self refresh mode, refresh interval and refresh operation are performed internally.
No precharge commands are required after Auto Refresh command.
During t
After self refresh entry, self refresh mode is kept while CKE is LOW.
During self refresh mode, all inputs expect CKE will be don’t cared, and outputs will be in Hi-Z state.
During t
Before/After self refresh mode, burst auto refresh cycle (4K cycles ) is recommended.
(Interrupted by Precharge)
Random column Access
Sequential counting
Interleave counting
CAS
RAS Interrupt
RC
RC
t
CCD
from auto refresh command, any other command can not be accepted.
from self refresh exit command, any other command can not be accepted.
BRSW
= 1 CLK
Interrupt
1
2
4
8
At MRS A3=”0”. See the BURST SEQUENCE TABE.(BL=4,8)
BL=1,2,4,8 and full page wrap around.
At MRS A3=” 1”. See the BURST SEQUENCE TABE.(BL=4,8)
BL=4,8 At BL=1,2 Interleave Counting = Sequential Counting
Every cycle Read/Write Command with random column address can realize
Random Column Access.
That is similar to Extended Data Out (EDO) Operation of convention DRAM.
At MRS A2,1,0 = “000”.
At auto precharge, tRAS should not be violated.
At MRS A2,1,0 = “001”.
At auto precharge, tRAS should not be violated.
At MRS A9=”1”.
Read burst = 1,2,4,8, full page/write Burst =1
At auto precharge of write, tRAS should not be violated.
Before the end of burst, Row precharge command of the same bank
Stops read/write burst with Row precharge.
t
During read/write burst with auto precharge, RAS interrupt cannot be issued.
Before the end of burst, new read/write stops read/write burst and starts new
read/write burst or block write.
During read/write burst with auto precharge,
At MRS A2,1,0 = “010”
At MRS A2,1,0 = “011”.
RDL
=1 with DQM, valid DQ after burst stop is 1,2 for CL=2,3 respectively
20
CAS
AMIC Technology, Corp.
interrupt can not be issued.
A43L3616A Series