H27UAG8T2ATR-BC HYNIX SEMICONDUCTOR, H27UAG8T2ATR-BC Datasheet - Page 53

• Manufacturer Part Number: H27UAG8T2ATR-BC
• Description: 58T1891
• Manufacturer: HYNIX SEMICONDUCTOR

Specifications of H27UAG8T2ATR-BC

• Memory Type: Flash - NAND
• Memory Size: 16Gbit
• Memory Configuration: 2048M X 8
• Supply Voltage Range: 2.7V To 3.6V
• Memory Case Style: TSOP
• No. Of Pins: 48
• Operating Temperature Range: 0°C To +70°C
• Rohs Compliant: Yes

Rev 1.0 / Aug. 2010
Note:
70h command is prohibited during interleaved operations.
5.3. Interleaved Page Program
Figure 53 show how to perform interleaved PROGRAM PAGE operations. RANDOM DATA INPUT (85h) is permitted
during interleaved PROGRAM PAGE operations.
Note:
70h command is prohibited during interleaved operations.
5.4. Interleaved Multi Plane Page Program
Figure 54 shows how to perform interleaved Multi Plane Page Program operations. The interleaved TWO-PLANE PRO-
GRAM PAGE operation must meet two-plane addressing requirements. Random data input (85h) is permitted during
interleaved Multi plane page program operation.
■ Figure 52. Interleaved multi plane page read
■ Figure 53. Interleaved page program
I/Ox
R/B#
R/B#
R/B#
I/Ox
R/B#
R/B#
R/B#
I/Ox
(chip 1 internal)
(chip 2 internal)
(external)
(chip 1 internal)
(chip 2 internal)
(external)
R/B#
R/B#
R/B#
(chip 1 internal)
(external)
(chip 2 internal)
80h
A
60h
00h
Address
(5cycle)
Address
(3cycle)
Chip 1
Chip 1
Address
(5cycle)
60h
Data Input
05h
Chip 1. plane 0
Address
(5cycle)
Chip 1
Address
(2cycle)
30h
10h
E0h
Chip 1. plane 0
60h
Data output
80h
Address
(3cycle)
Chip 2
Address
(5cycle)
Chip 2
60h
78h
Add.1
Address
Row
(3cycle)
Chip 2
Chip 2
Data Input
Add.2
Row
30h
Add.3
Row
Status
10h
78h
Chip 1
Add.1
Row
00h
78h
Add.2
Address
(5cycle)
Row
Add.1
Chip 1
Row
Add.3
Row
16Gb (2048M x 8bit) NAND Flash
05h
Add.2
Row
Status
Chip 2. plane 0
Address
(2cycle)
Add.3
Row
00h
E0h
Chip 1, plane 0
Status
Address
(5cycle)
Chip 2. plane 0
Data output
05h
80h
Chip 1, plane 0
H27UAG8T2B Series
Address
(2cycle)
00h
Address
(5cycle)
Chip 1
Address
(5cycle)
E0h
Chip 1, plane 0
Data Input
Data output
05h
Chip 2. plane 1
Address
(2cycle)
A
10h
E0h
Release
Chip 2. plane 1
Data output
53