TE28F800C3TA90 Intel, TE28F800C3TA90 Datasheet
TE28F800C3TA90
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TE28F800C3TA90 Summary of contents
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... Memory (C3) products will be available in 48-lead TSOP, 48-ball CSP, and 64-ball Easy BGA packages. Additional information on this product family can be obtained by accessing the Intel Flash website: http://www.intel.com/design/flash. Notice: This specification is subject to change without notice. Verify with your local Intel sales office that you have the latest datasheet before finalizing a design. Datasheet 128-bit Protection Register — ...
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... Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800- 548-4725 or by visiting Intel's website at http://www.intel.com. ...
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Contents 1.0 Introduction....................................................................................................................................7 1.1 Document Purpose ...............................................................................................................7 1.2 Nomenclature .......................................................................................................................7 1.3 Conventions..........................................................................................................................7 2.0 Device Description ........................................................................................................................8 2.1 Product Overview .................................................................................................................8 2.2 Ballout Diagram ....................................................................................................................8 2.3 Signal Descriptions .............................................................................................................13 2.4 Block Diagram ....................................................................................................................14 2.5 Memory Map .......................................................................................................................15 3.0 Device Operations .......................................................................................................................17 ...
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Contents 5.6.1 Program Protection................................................................................................ 31 6.0 Power Consumption.................................................................................................................... 32 6.1 Active Power (Program/Erase/Read).................................................................................. 32 6.2 Automatic Power Savings (APS) ........................................................................................ 32 6.3 Standby Power ................................................................................................................... 32 6.4 Deep Power-Down Mode.................................................................................................... 32 6.5 Power and Reset Considerations ....................................................................................... 33 6.5.1 Power-Up/Down ...
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Revision History Date of Version Revision 05/12/98 -001 07/21/98 -002 10/03/98 -003 12/04/98 -004 12/31/98 -005 02/24/99 -006 06/10/99 -007 03/20/00 -008 04/24/00 -009 10/12/00 -010 7/20/01 -011 10/02/01 -012 2/05/02 -013 Datasheet Description Original version 48-Lead TSOP package diagram ...
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Contents Date of Version Revision 4/05/02 -014 3/06/03 -016 10/03 -017 6 Description Updated 64Mb product offerings. Updated 16Mb product offerings. Revised and corrected DC Characteristics Table. Added mechanicals for Easy BGA. Minor text edits throughout document. Complete technical update. ...
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... Introduction 1.1 Document Purpose This datasheet contains the specifications for the Intel (C3) device family. These flash memories add features such as instant block locking and protection registers that can be used to enhance the security of systems. 1.2 Nomenclature Hexadecimal prefix 0x 0b Binary prefix ...
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... Intel Advanced+ Boot Block Flash Memory (C3) 2.0 Device Description This section provides an overview of the Intel features, packaging, signal naming, and device architecture. 2.1 Product Overview The C3 device provides high-performance asynchronous reads in package-compatible densities with a 16 bit data bus. Individually-erasable memory blocks are optimally sized for code and data storage. Eight 4 Kword parameter blocks are located in the boot block at either the top or bottom of the device’ ...
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... Figure 1. 48-Lead TSOP Package WE NOTES: 1. For lower densities, upper address should be treated as NC. For example, a 16-Mbit device will have NC on Pins 9 and 10. Datasheet £ Intel Advanced+ Boot Block Flash Memory (C3 Advanced+ Boot Block 11 48-Lead TSOP TOP VIEW CCQ 46 GND OE# ...
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... TSOP Extended 64 Mbit TE28F640C3TC80 TE28F320C3TD70 TE28F640C3BC80 TE28F320C3BD70 TE28F320C3TC70 TE28F320C3BC70 TE28F320C3TC90 TE28F320C3BC90 TE28F320C3TA100 TE28F320C3BA100 TE28F320C3TA110 TE28F320C3BA110 10 £ Advanced and Advanced + Boot Block Extended 32 Mbit Extended 16 Mbit TE28F160C3TD70 TE28F160C3BD70 TE28F160C3TC80 TE28F160C3BC80 TE28F160C3TA90 TE28F160C3BA90 TE28F160C3TA110 TE28F160C3BA110 Extended 8 Mbit TE28F800C3TA90 TE28F800C3BA90 TE28F800C3TA110 TE28F800C3BA110 Datasheet ...
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... F GND D7 NOTES: 1. Shaded connections indicate the upgrade address connections. Routing is not recommended in this area. 2. A19 denotes 16 Mbit; A20 denotes 32 Mbit; A21 denotes 64 Mbit. 3. Unused address balls are not populated. Datasheet £ Intel Advanced+ Boot Block Flash Memory (C3) 1,2 16M A8 VPP WP# ...
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... Intel Advanced+ Boot Block Flash Memory (C3) Figure 4. 64-Ball Easy BGA Package ( RP WP SSQ ( CCQ CC SSQ Top View - Ball Side NOTES: 1. A19 denotes 16 Mbit; A20 denotes 32 Mbit; A21 denotes 64 Mbit. 2. Unused address balls are not populated GND ( ( SSQ ...
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... CONNECT: Pin must be left floating. Datasheet £ Intel Advanced+ Boot Block Flash Memory (C3) Name and Function for details on block locking. VPPLK to protect all contents against Program and Erase commands. 5% for faster program and erase in a production environment. Applying range ...
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... Intel Advanced+ Boot Block Flash Memory (C3) 2.4 Block Diagram V CCQ A[MAX:MIN] Input Buffer Address Latch Address Counter Output Buffer Identifier Register Status Register Power Data Reduction Comparator Control Y-Decoder Y-Gating/Sensing X-Decoder Input Buffer I/O Logic CE# Command WE# User OE# Interface RP# ...
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... Datasheet £ Intel Advanced+ Boot Block Flash Memory (C3) 16-Mbit Memory Size Blk Blk Addressing (KW) Addressing (HEX) 38 FF000-FFFFF FE000-FEFFF FD000-FDFFF FC000-FCFFF FB000-FBFFF FA000-FAFFF F9000-F9FFF F8000-F8FFF F0000-F7FFF E8000-EFFFF 32 ...
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... Intel Advanced+ Boot Block Flash Memory (C3) Table 4. Bottom Boot Memory Map 8-Mbit Size Memory Size Blk Blk (KW) Addressing (KW) (HEX 78000-7FFFF 70000-77FFF 68000-6FFFF 60000-67FFF 32 ... ... ... ... 32 10 18000-1FFFF 10000-17FFF 08000-0FFFF 07000-07FFF 06000-06FFF 05000-05FFF 04000-04FFF 03000-03FFF 02000-02FFF 01000-01FFF 00000-00FFF 4 16 16-Mbit Memory Size Blk ...
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... Address and data are latched on the rising edge of the WE# or CE# pulse, whichever occurs first. See Figure 9, “Write Operations Waveform” on page 3.1.3 Output Disable With OE logic - high level (V high - impedance state. Datasheet £ Intel Advanced+ Boot Block Flash Memory (C3) summarizes these bus operations. Mode RP# CE ...
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... Block-Erase operations CPU reset occurs with no flash memory reset, proper CPU initialization may not occur because the flash memory may be providing status information instead of array data. Intel allow proper CPU initialization following a system reset through the use of the RP# input. In this application, RP# is controlled by the same RESET# signal that resets the system CPU ...
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... Read Identifier command (0x90). Once in this mode, read cycles from addresses shown in retrieve the specified information. To return to read-array mode, issue the Read Array command (0xFF). Datasheet £ Intel Advanced+ Boot Block Flash Memory (C3) and Table 8, “Command Codes and summarize the commands used to reach these modes. ...
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... Intel Advanced+ Boot Block Flash Memory (C3) Table 6. Device Identification Codes Item Manufacturer ID Device ID 2 Block Lock Status Block Lock-Down Status Protection Register Lock Status Protection Register NOTES: 1. The address is constructed from a base address plus an offset. For example, to read the Block Lock Status for block number bottom boot device, set the address to 0x0F8000 plus the offset (0x02), i ...
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... VPP pin. This eliminates the need for an external switching transistor to control V flash power supplies can be configured for various usage models. Datasheet £ Intel Advanced+ Boot Block Flash Memory (C3) 26). was not within acceptable limits, and the WSM did not execute the program PP is driven by a logic signal, V min = 1 ...
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... Intel Advanced+ Boot Block Flash Memory (C3) The mode enhances programming performance during the short period of time typically PP found in manufacturing processes; however not intended for extended use may be applied to VPP during Program and Erase operations for a maximum of 1000 cycles on the main blocks and 2500 cycles on the parameter blocks ...
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... CE consumption. Erase Resume continues the erase sequence when CE Erase operation, the status register should be read and cleared before the next instruction is issued. Datasheet £ Intel Advanced+ Boot Block Flash Memory (C3 EHRH2 , which reduces active current IH ...
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... NOTES: 1. Following the Read Identifier or CFI Query commands, read operations output device identification data or CFI query information, respectively. See 2. Either 0x40 or 0x10 command is valid, but the Intel standard is 0x40. 3. When writing commands, the upper data bus [DQ8-DQ15] should be either V draw. Bus operations are defined in ...
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... WSM to execute the Protection Program algorithm to the protection register. The flash outputs Set-Up status-register data when CE# or OE# is toggled. A Read Array command is required after programming to read array data. See Datasheet £ Intel Advanced+ Boot Block Flash Memory (C3) Command Description 21. Section 4.3, “Erase Mode” on page Section 5 ...
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... Device Mode (HEX) 10 Alt. Prog Set-Up Operates the same as Program Set - up command. (See 0x40/Program Set-Up) Invalid/ Unassigned commands should not be used. Intel reserves the right to redefine these codes for 00 Reserved future functions. NOTE: See Appendix A, “Write State Machine States” Table 9. ...
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... D0 indicates block lock status ‘0’, block is unlocked ‘1’, block is locked. 4. Locked-down = Hardware + Software locked. 5. [011] states should be tracked by system software to determine difference Datasheet £ Intel Advanced+ Boot Block Flash Memory (C3) displays all of the possible locking states. Locked- Locked ...
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... Intel Advanced+ Boot Block Flash Memory (C3) 5.1.1 Locking Operation The locking status of each block can be set to Locked, Unlocked, or Lock-Down, each of which will be described in the following sections. See page 27 and Figure 17, “Locking Operations Flowchart” on page The following concisely summarizes the locking functionality. ...
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... Boot Block Flash Memory Architecture, contains additional application information. The 128 bits of the protection register are divided into two 64-bit segments. One of the segments is programmed at the Intel factory with a unique 64-bit number, which is unchangeable. The other segment is left blank for customer designs to program, as preferred. Once the customer segment is programmed, it can be locked to prevent further programming ...
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... The user-programmable segment of the protection register is lockable by programming bit 1 of the PR-LOCK location to 0. See location is programmed the Intel factory to protect the unique device number. This bit is set using the Protection Program command to program 0xFFFD to the PR-LOCK location. After these bits have been programmed, no further changes can be made to the values stored in the protection register ...
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... Low Voltage and 12 V Fast Programming NOTE resistor can be used if the V Designing with the Advanced+ Boot Block Flash Memory Architecture for details. Datasheet £ Intel Advanced+ Boot Block Flash Memory (C3) programming voltage can be held low for absolute PP System Supply System Supply ...
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... Power Consumption Intel Flash devices have a tiered approach to power savings that can significantly reduce overall system power consumption. The Automatic Power Savings (APS) feature reduces power consumption when the device is selected but idle. If CE# is deasserted, the flash enters its standby mode, where current consumption is even lower ...
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... If a CPU reset occurs without a flash memory reset, proper CPU initialization will not occur because the flash memory may be providing status information instead of array data. Intel recommends connecting RP# to the system CPU RESET# signal to allow proper CPU/flash initialization following system reset. ...
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... These are stress ratings only. Operation beyond the “Operating Conditions” is not recommended, and extended exposure beyond the “Operating Conditions” may affect device reliability. . NOTICE: Specifications are subject to change without notice. Verify with your local Intel Sales office that you have the latest datasheet before finalizing a design Extended Operating Temperature ...
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... V 80 hours maximum. 7.3 DC Current Characteristics Table 11. DC Current Characteristics (Sheet Sym Parameter I Input Load Current LI Output Leakage I LO Current Datasheet £ Intel Advanced+ Boot Block Flash Memory (C3) Parameter Notes may be connected for a total 2.7 V–3.6 V 2.7 V–2. 2.7 V– ...
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... Intel Advanced+ Boot Block Flash Memory (C3) Table 11. DC Current Characteristics (Sheet Sym Parameter V Standby Current CC for 0.13 and 0.18 Micron Product I CCS V Standby Current CC for 0.25 Micron Product V Power-Down CC Current for 0.13 and 0.18 Micron Product I CCD V Power-Down CC Current for 0.25 ...
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... specified with device de-selected. If device is read while in erase suspend, current draw CCES CCWS is sum of I and I CCES and I . CCR Datasheet £ Intel Advanced+ Boot Block Flash Memory (C3) V 2.7 V–3.6 V 2.7 V–2. 2.7 V–3.6 V 1.65 V–2.5 V CCQ Note Typ Max Typ ...
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... Intel Advanced+ Boot Block Flash Memory (C3) 7.4 DC Voltage Characteristics Table 12. DC Voltage Characteristics V 2.7 V–3 Sym Parameter V 2.7 V–3.6 V CCQ Note Min Input Low V –0.4 IL Voltage Input High V 2.0 IH Voltage Output Low V –0.1 OL Voltage Output High V CCQ V OH Voltage –0.1V ...
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... ELQV– GLQV 2. Sampled, but not 100% tested. 3. See Figure 8, “Read Operation Waveform” on page 4. See Figure 11, “AC Input/Output Reference Waveform” on page 49 slew rate. Datasheet £ Intel Advanced+ Boot Block Flash Memory (C3) Density Product 3.0 V – 3.6 V 2.7 V – 3 Note ...
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... Intel Advanced+ Boot Block Flash Memory (C3) Table 14. Read Operations—16 Mbit Density Density 70 ns Product Para- # Sym mete r 2.7 V–3 Min Read Cycle Time AVAV t Address to AVQ R2 Output Delay V t CE# to Output ELQ R3 Delay V t OE# to Output GLQ R4 Delay V t RP# to Output ...
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... Sampled, but not 100% tested. 3. See Figure 8, “Read Operation Waveform” on page 4. See Figure 11, “AC Input/Output Reference Waveform” on page 49 input slew rate. Datasheet £ Intel Advanced+ Boot Block Flash Memory (C3) 32 Mbit 90 ns 100 ns 2.7 V–3.6 V 3.0 V–3.3 V 2.7 V–3.3 V ...
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... Intel Advanced+ Boot Block Flash Memory (C3) Table 16. Read Operations — 64 Mbit Density # Sym R1 t Read Cycle Time AVAV R2 t Address to Output Delay AVQV R3 t CE# to Output Delay ELQV R4 t OE# to Output Delay GLQV R5 t RP# to Output Delay PHQV R6 t CE# to Output in Low Z ...
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... Table 7, “Command Bus Operations” on page 24 3. Sampled, but not 100% tested. 4. See Figure 11, “AC Input/Output Reference Waveform” on page 49 slew rate. 5. See Figure 9, “Write Operations Waveform” on page Datasheet £ Intel Advanced+ Boot Block Flash Memory (C3) Density Product 3.0 V – 3 2.7 V – 3.6 V Note ...
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... Intel Advanced+ Boot Block Flash Memory (C3) Table 18. Write Operations—16 Mbit Density # Sym Parameter t / RP# High Recovery to WE# (CE#) Going PHWL W1 t Low PHEL t / ELWL W2 CE# (WE#) Setup to WE# (CE#) Going Low t WLEL t / WLWH W3 WE# (CE#) Pulse Width t ELEH t / DVWH W4 Data Setup to WE# (CE#) Going High ...
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... Sampled, but not 100% tested. 4. See Figure 11, “AC Input/Output Reference Waveform” on page 49 slew rate. 5. See Figure 9, “Write Operations Waveform” on page 6. V Max = 3.3 V for 32-Mbit 0.25 Micron product. CC Datasheet £ Intel Advanced+ Boot Block Flash Memory (C3) Density Product 3.0 V – 3 2.7 V – 3.6 V ...
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... Intel Advanced+ Boot Block Flash Memory (C3) Table 20. Write Operations—64Mbit Density # Sym t / PHWL W1 RP# High Recovery to WE# (CE#) Going Low t PHEL t / ELWL W2 CE# (WE#) Setup to WE# (CE#) Going Low t WLEL t / WLWH W3 WE# (CE#) Pulse Width t ELEH t / DVWH W4 Data Setup to WE# (CE#) Going High t DVEH t / AVWH ...
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... WHQV3 EHQV3 Erase Time Program Suspend Latency WHRH1 EHRH1 Erase Suspend Latency WHRH2 EHRH2 NOTES: 1. Typical values measured Excludes external system-level overhead. 3. Sampled, but not 100% tested. Datasheet £ Intel Advanced+ Boot Block Flash Memory (C3 W10 V PP Parameter Note 1,3 1,3 = +25 ° ...
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... Intel Advanced+ Boot Block Flash Memory (C3) 8.4 Reset Specifications Table 22. Reset Specifications Symbol RP# Low to Reset during Read t (If RP# is tied to V PLPH applicable) t RP# Low to Reset during Block Erase PLRH1 t RP# Low to Reset during Program PLRH2 NOTES < 100 ns the device may still reset but this is not guaranteed. ...
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... NOTE: C includes jig capacitance. L 8.6 Device Capacitance ° MHz A Symbol Output Capacitance OUT § Sampled, not 100% tested. Datasheet £ Intel Advanced+ Boot Block Flash Memory (C3 CCQ /2. Input rise and fall times (10% to 90%) < 5 ns. CCQ = V Min Device Under Test (pF) ...
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... Intel Advanced+ Boot Block Flash Memory (C3) Appendix A Write State Machine States This table shows the command state transitions based on incoming commands. Data Read Array Current State SR.7 When (FFH) Read Read Array “1” Array Read Array Read Status “1” ...
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... Erase Suspend Erase Suspend Query Read Config. Read Query Ers.(Done) Read Config. Read Query Datasheet £ Intel Advanced+ Boot Block Flash Memory (C3) Command Input (and Next State) Lock Setup Prot. Prog. Lock Confirm (60H) Setup (C0H) (01H) Lock Setup Prot. Prog. Setup Lock Setup Prot ...
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... Intel Advanced+ Boot Block Flash Memory (C3) Appendix B Flow Charts Figure 13. Word Program Flowchart Start Write 0x40, Word Address Write Data, Word Address Read Status Register 0 SR[ Full Status Check (if desired) Program Complete Read Status Register 1 SR[ SR[ SR[ Program Successful 52 WORD PROGRAM PROCEDURE ...
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... Array) Read Array Data Done No Reading Yes Write 0xD0 (Program Resume) Any Address Program Resumed Datasheet £ Intel Advanced+ Boot Block Flash Memory (C3) PROGRAM SUSPEND / RESUME PROCEDURE Bus Operation Command Read Write Status Program Write Suspend Read None Idle None ...
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... Intel Advanced+ Boot Block Flash Memory (C3) Figure 15. Erase Suspend / Resume Flowchart Start Write 0xB0, Any Address Write 0x70, Any Address Read Status Register SR[7] = SR[6] = Write 0xFF Read Array (Read Array) Data Done Reading Write 0xD0, (Erase Resume) Any Address ...
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... Register 1 SR[ 1,1 SR[4, SR[ SR[ Block Erase Successful Datasheet £ Intel Advanced+ Boot Block Flash Memory (C3) BLOCK ERASE PROCEDURE Bus Operation Command Write Write Read Suspend Erase Loop Idle No Suspend Yes Erase Repeat for subsequent block erasures. Full Status register check can be done after each block erase or after a sequence of block erasures ...
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... Intel Advanced+ Boot Block Flash Memory (C3) Figure 17. Locking Operations Flowchart Start Write 0x60, Block Address Write either 0x01/0xD0/0x2F, Block Address Write 0x90 Read Block Lock Status Locking Change? Yes Write 0xFF Any Address Lock Change Complete 56 LOCKING OPERATIONS PROCEDURE Bus ...
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... Read Status Register Data SR[3], SR[ SR[3], SR[ SR[3], SR[ Program Successful Datasheet £ Intel Advanced+ Boot Block Flash Memory (C3) PROTECTION REGISTER PROGRAMMING PROCEDURE Bus Operation Write (Program Setup) Write (Confirm Data) Read Idle Program Protection Register operation addresses must be within the Protection Register address space. Addresses outside this space will return an error ...
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... Intel Advanced+ Boot Block Flash Memory (C3) Appendix C Common Flash Interface This appendix defines the data structure or “database” returned by the Common Flash Interface (CFI) Query command. System software should parse this structure to gain critical information such as block size, density, x8/x16, and electrical specifications. Once this information has been obtained, the software will know which command sets to use to enable flash writes, block erases, and otherwise control the flash component ...
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... BA = Block Address beginning location (i.e., 0x08000 is block 1’s beginning location when the block size is 32K-word). 3. Offset 15 defines “P” which points to the Primary Intel-specific Extended Query Table. C.3 Block Status Register The Block Status Register indicates whether an erase operation completed successfully or whether a given block is locked or can be accessed for flash program/erase operations ...
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... Intel Advanced+ Boot Block Flash Memory (C3) Table 27. Block Status Register Offset Length 1 0x(BA+2) 1 NOTES Block Address beginning location (i.e., 0x08000 is block 1’s beginning location when the block size is 32K-word). C.4 CFI Query Identification String The Identification String provides verification that the component supports the Common Flash Interface specification ...
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... Erase Block Region 2 Information bits 0– y+1 = number of identical-size erase blocks 0x2D 14 bits 16– region erase block(s) size are z x 256 bytes Datasheet £ Intel Advanced+ Boot Block Flash Memory (C3) Description n µs n µs n ...
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... C.6 Intel-Specific Extended Query Table Certain flash features and commands are optional. The Intel - Specific Extended Query table specifies this and other similar types of information. Table 32. Primary-Vendor Specific Extended Query (Sheet Offset Length P = 0x15 (Optional Flash Features and Commands) ...
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... Lock/bytes JEDEC -plane physical high address bits 16–23 = “n” such that 2 bits 24–31 = “n” such that 2 0x(P+13) Reserved for future use NOTES: 1. The variable pointer which is defined at CFI offset 0x15. Datasheet £ Intel Advanced+ Boot Block Flash Memory (C3) Description Address 3E: 3F: 40: 41: 42: ...
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... Intel Advanced+ Boot Block Flash Memory (C3) Appendix D Mechanical Specifications Figure 19. BGA* and VF BGA Package Drawing & Dimensions Ball A1 Corner Top View - Bump Side down Dimensions Package Height Ball Height Package Body Thickness Ball (Lead) Width Package Body Length 8M (.25) Package Body Length 16M (.25/.18/.13) 32M (.25/.18/.13) Package Body Length 64M ( ...
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... If two dimples, then the larger dimple denotes Pin 1. 3. Pin 1 will always be in the upper left corner of the package, in reference to the product mark. 4. Pin 1 will always supersede above pin one notes. Datasheet £ Intel Advanced+ Boot Block Flash Memory (C3) See Notes and ...
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... Intel Advanced+ Boot Block Flash Memory (C3) Figure 21. Easy BGA Package Drawing & Dimension Ball A1 Corner Top View - Ball side down A1 A2 Dimensions Table Package Height Ball Height Package Body Thickness Ball (Lead) Width Package Body Width Package Body Length Pitch ...
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... Contact your Intel Representative 297874 NOTES: 1. Please call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International customers should contact their local Intel or distribution sales office. 2. Visit Intel’s World Wide Web home page at ‘http://www.intel.com/design/flash’ for technical documentation and tools. ...
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... Mbit TE28F160C3TC90 TE28F160C3BC90 TE28F160C3TA90 TE28F160C3BA90 TE28F160C3TA110 TE28F160C3BA110 TE28F800C3TA90 TE28F800C3BA90 Extended 8 Mbit TE28F800C3TA110 TE28F800C3BA110 NOTE: The second line of the 48-ball µBGA package top side mark specifies assembly codes. For samples only, the first character signifies either “E” for engineering samples or “S” for silicon daisy chain samples. All other assembly codes without an “ ...