MT4LC16M4H9DJ-5 Micron Technology Inc, MT4LC16M4H9DJ-5 Datasheet - Page 20

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MT4LC16M4H9DJ-5

Manufacturer Part Number
MT4LC16M4H9DJ-5
Description
DRAM Chip EDO 64M-Bit 16Mx4 3.3V 32-Pin SOJ Tray
Manufacturer
Micron Technology Inc
Type
EDOr
Datasheet

Specifications of MT4LC16M4H9DJ-5

Package
32SOJ
Density
64 Mb
Address Bus Width
12 Bit
Operating Supply Voltage
3.3 V
Maximum Random Access Time
50 ns
Operating Temperature
0 to 70 °C
TIMING PARAMETERS
NOTE: 1. Once
16 Meg x 4 EDO DRAM
D22_2.p65 – Rev. 5/00
SYMBOL
t
t
t
t
t
CHD
CP
CSR
RASS
RP
RAS#
CAS#
WE#
DQ
2. Once
V
V
V
V
V
V
V
V
OH
OL
IH
IL
IH
IL
IH
IL
t
t
RASS (MIN) is met and RAS# remains LOW, the DRAM will enter self refresh mode.
RPS is satisfied, a complete burst of all rows should be executed if RAS#-only por Burst CBR refresh is being used.
MIN
100
15
30
8
5
t RP
t RPC
t CP
-5
MAX
t WRP
t CSR
MIN
t RASS
t CHD
t WRH
100
15
10
40
5
(Addresses and OE# = DON’T CARE)
-6
MAX
(
(
)
)
(
(
(
(
(
)
)
)
)
)
(
(
)
)
(
(
(
(
(
)
)
)
)
)
SELF REFRESH CYCLE
OPEN
UNITS
ns
ns
ns
µs
ns
20
SYMBOL
t
t
t
t
RPC
RPS
WRH
WRP
Micron Technology, Inc., reserves the right to change products or specifications without notice.
NOTE 1
t RPC
t RPS
MIN
90
5
8
8
t CP
t WRP
-5
MAX
t WRH
NOTE 2
(
)
(
MIN
)
105
10
10
5
16 MEG x 4
EDO DRAM
-6
DON’T CARE
UNDEFINED
©2000, Micron Technology, Inc.
MAX
OBSOLETE
UNITS
ns
ns
ns
ns

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