MT4LC16M4H9DJ-5 Micron Technology Inc, MT4LC16M4H9DJ-5 Datasheet - Page 3

• Manufacturer Part Number: MT4LC16M4H9DJ-5
• Description: DRAM Chip EDO 64M-Bit 16Mx4 3.3V 32-Pin SOJ Tray
• Manufacturer: Micron Technology Inc
• Type: EDOr

Specifications of MT4LC16M4H9DJ-5

• Package: 32SOJ
• Density: 64 Mb
• Address Bus Width: 12 Bit
• Operating Supply Voltage: 3.3 V
• Maximum Random Access Time: 50 ns
• Operating Temperature: 0 to 70 °C

uniquely addressed via the address bits. First, the row
address is latched by the RAS# signal, then the column
address is latched by CAS#. The device provides EDO-
PAGE-MODE operation, allowing for fast successive
data operations (READ, WRITE, or READ-MODIFY-
WRITE) within a given row.
in order to retain stored data.
DRAM ACCESS
as mentioned in the General Description. The data for
each location is accessed via the four I/O pins (DQ0-
DQ3). A logic HIGH on WE# dictates read mode, while
a logic LOW on WE# dictates write mode. During a
WRITE cycle, data-in (D) is latched by the falling edge
of WE# or CAS#, whichever occurs last. An EARLY
WRITE occurs when WE# is taken LOW prior to CAS#
falling. A LATE WRITE or READ-MODIFY-WRITE occurs
when WE# falls after CAS# is taken LOW. During
EARLY WRITE cycles, the data outputs (Q) will remain
High-Z, regardless of the state of OE#. During LATE
WRITE or READ-MODIFY-WRITE cycles, OE# must be
taken HIGH to disable the data outputs prior to apply-
ing input data. If a LATE WRITE or READ-MODIFY-
WRITE is attempted while keeping OE# LOW, no WRITE
will occur, and the data outputs will drive read data
from the accessed location.
EDO PAGE MODE
output buffers off (High-Z) with the rising edge of
CAS#. If CAS# went HIGH and OE# was LOW (active),
the output buffers would be disabled. The 16 Meg x 4
DRAM offers an accelerated page mode cycle by elimi-
nating output disable from CAS# HIGH. This option is
called EDO and it allows CAS# precharge time (
occur without the output data going invalid (see READ
and EDO-PAGE-MODE READ waveforms).
MODE READ, except data is held valid after CAS# goes
HIGH, as long as RAS# and OE# are held LOW and WE#
is held HIGH. OE# can be brought LOW or HIGH while
CAS# and RAS# are LOW, and the DQs will transition
between valid data and High-Z. Using OE#, there are
two methods to disable the outputs and keep them
disabled during the CAS# HIGH time. The first method
is to have OE# HIGH when CAS# transitions HIGH and
keep OE# HIGH for
the DQs, and they will remain disabled (regardless of
the state of OE# after that point) until CAS# falls again.
The second method is to have OE# LOW when CAS#
16 Meg x 4 EDO DRAM
D22_2.p65 – Rev. 5/00
GENERAL DESCRIPTION (Continued)
The 16 Meg x 4 DRAM must be refreshed periodically
Each location in the DRAM is uniquely addressable,
DRAM READ cycles have traditionally turned the
EDO operates like any DRAM READ or FAST-PAGE-
t
OEHC thereafter. This will disable
t
CP) to
3
transitions HIGH and then bring OE# HIGH for a
minimum of
period. This will disable the DQs, and they will remain
disabled (regardless of the state of OE# after that point)
until CAS# falls again. (Please refer to Figure 1.) During
other cycles, the outputs are disabled at
RAS# and CAS# are HIGH or at
tions LOW. The
edge of RAS# or CAS#, whichever occurs last. WE# can
also perform the function of disabling the output
drivers under certain conditions, as shown in Figure 2.
with a row address strobed in by the RAS# signal,
followed by a column address strobed in by CAS#, just
like for single location accesses. However, subsequent
column locations within the row may then be accessed
at the page mode cycle time. This is accomplished by
cycling CAS# while holding RAS# LOW and entering
new column addresses with each CAS# cycle. Returning
RAS# HIGH terminates the EDO-PAGE-MODE opera-
tion.
DRAM REFRESH
fied levels, and the refresh requirements must be met in
order to retain stored data in the DRAM. The refresh
requirements are met by refreshing all 8,192 rows (G3)
or all 4,096 rows (H9) in the DRAM array at least once
every 64ms. The recommended procedure is to execute
4,096 CBR REFRESH cycles, either uniformly spaced or
grouped in bursts, every 64ms. The MT4LC16M4G3
internally refreshes two rows for every CBR cycle,
whereas the MT4LC16M4H9 refreshes one row for
every CBR cycle. So with either device, executing 4,096
CBR cycles covers all rows. The CBR refresh will invoke
the internal refresh counter for automatic RAS# ad-
dressing. Alternatively, RAS#-ONLY REFRESH capabil-
ity is inherently provided. However, with this method,
some compatibility issues may become apparent. For
example, both G3 and H9 versions require 4,096 CBR
REFRESH cycles, yet each requires a different number of
RAS#-ONLY REFRESH cycles (G3 = 8,192 and H9 =
4,096). JEDEC strongly recommends the use of CBR
REFRESH for this device.
“S” version. The self refresh feature is initiated by
performing a CBR REFRESH cycle and holding RAS#
LOW for the specified
an extended refresh period of 128ms, or 31.25µs per
row for a 4K refresh and 15.625µs per row for an 8K
refresh, when using a distributed CBR REFRESH. This
refresh rate can be applied during normal operation, as
well as during a standby or battery backup mode.
EDO-PAGE-MODE operations are always initiated
The supply voltage must be maintained at the speci-
An optional self refresh mode is also available on the
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
OEP anytime during the CAS# HIGH
t
OFF time is referenced from the rising
t
RASS. The “S” option allows for
t
WHZ after WE# transi-
16 MEG x 4
EDO DRAM
©2000, Micron Technology, Inc.
t
OFF time after
OBSOLETE