P87C554SBAA NXP Semiconductors, P87C554SBAA Datasheet - Page 67

• Manufacturer Part Number: P87C554SBAA
• Description: MCU 8-Bit 87C 80C51 CISC 16KB EPROM 5V 68-Pin PLCC Tube
• Manufacturer: NXP Semiconductors

Specifications of P87C554SBAA

• Package: 68PLCC
• Device Core: 80C51
• Family Name: 87C
• Maximum Speed: 16 MHz
• Ram Size: 512 Byte
• Program Memory Size: 16 KB
• Operating Supply Voltage: 5 V
• Data Bus Width: 8 Bit
• Program Memory Type: EPROM
• Number Of Programmable I/os: 40
• Interface Type: I2C/UART
• On-chip Adc: 7-chx10-bit
• Operating Temperature: 0 to 70 °C
• Number Of Timers: 3

1. At 100 kbit/s. At other bit rates this value is inversely proportional to the bit-rate of 100 kbit/s.
2. Determined by the external bus-line capacitance and the external bus-line pull-resistor, this must be < 1 s.
3. Spikes of the SDA and SCL lines with a duration of less than 3 t
4. t
5. These values are guaranteed but not 100% production tested.
6. See application note AN457 for external memory interface.
7. Parts are guaranteed to operate down to 0Hz.
Philips Semiconductors
Table 11. I
All values referred to V
NOTES
2003 Jan 28
80C51 8-bit microcontroller – 6-clock operation
16K/512 OTP/ROMless, 7 channel 10 bit A/D, I
high I/O, 64L LQFP
t
t
t
t
t
t
t
t
t
t
t
t
t
t
SCL = 400 pF.
I
HD;STA
LOW
HIGH
RC
FC
SU;DAT1
SU;DAT2
SU;DAT3
HD;DAT
SU;STA
SU;STO
BUF
RD
FD
CLK
2
C-bus specification for bit-rates up to 100 kbit/s.
= 1/f
SYMBOL
CLK
2
C-bus interface timing
= one oscillator clock period at pin XTAL1. For 83 ns < t
IH(min)
and V
PARAMETER
START condition hold time
LOW period of the SCL clock
HIGH period of the SCL clock
Rise time of SCL signals
Fall time of SCL signals
Data set-up time
SDA set-up time (before repeated START condition)
SDA set-up time (before STOP condition)
Data hold time
Set-up time for a repeated START condition
Set-up time for STOP condition
Bus free time between
Rise time of SDA signals
Fall time of SDA signals
IL(max)
levels; see Figure 56
5
.
CLK
2
C, PWM, capture/compare,
67
will be filtered out. Maximum capacitance on bus-lines SDA and
CLK
< 285 ns (12 MHz > f
CLK
> 3.5 MHz) the SI01 interface meets the
INPUT
250 ns
250 ns
250 ns
7 t
8 t
7 t
0.3 s
7 t
7 t
7 t
0.3 s
1 s
0 ns
1 s
CLK
CLK
CLK
CLK
CLK
CLK
I
2
C-BUS
80C554/87C554
> 10 t
> 4 t
OUTPUT
> 4.0 s
> 4.7 s
> 4.0 s
< 0.3 s
> 4.7 s
> 4.0 s
> 4.7 s
< 0.3 s
> 4 t
> 1 s
CLK
Product data
–
CLK
–
2
2
CLK
–t
–t
1
1
1
1
3
1
1
1
3
FC
RD